Chip Design Resources

Sort by

Synopsys Suggests

10 Ways to Effectively Debug your FPGA Design

Oct 2012 - FPGAs implement the equivalent of millions of ASIC gates and continue to grow in size and complexity. With the increasing amount of time designers are spending debugging and diagnosing ...

2018 TSMC Technology Symposium

2018 TSMC Technology Symposium

3D Extraction Necessities for 5nm and Below

Jan 25, 2018 - New transistor architectures mean new parasitic effects to watch out for.

7/5nm Timing Closure Intensifies

Jan 25, 2018 - The issues may be familiar, but they’re more difficult to solve and can affect everything from performance to yield.

A Safe Approach to Hierarchical UPF Verification in Formality

The IEEE-1801 IEEE Standard for Design and Verification of LowPower Integrated Circuits (UPF) adds additional constraints on the design affecting synthesis and verification. Using Formality with ...

Abilis Systems Achieves First-Pass Silicon Success for Secure Media Processor...

Oct 2013 - Abilis Achieves First-Pass Silicon Success for Secure Media Processor Using Synopsys DesignWare IP and Lynx Design System

Accelerate FPGA Design Performance and Advanced Constraint Development

Jan 25, 2017 - Using Synplify Premier, learn how to setup a design, quickly find RTL compile errors, initially define constraints and tune the design for best performance

Accelerate FPGA Design Performance with Advanced Constraint Development ...

Jul 19, 2017 - Using Synplify Premier, learn how to setup a design, quickly find RTL compile errors, initially define constraints and tune the design for best performance.

Accelerated Optimization with IC Compiler II

Sep 2014 - Efficient optimization is a necessary yet challenging aspect of the physical implementation flow. Newer nodes and growing designs are all conspiring to place growing demands on this ...

Accelerated Synthesis Runtimes Increase Productivity

Dec 17, 2015 - As FPGAs grow ever bigger and more complex, hard-working synthesis tools are stepping up to help designers find optimum solutions for balancing runtime and quality of results