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DFTMAX Compression Shared I/O

Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs

Synopsys Fusion Technology Enables Lower Power, Smaller Area, and Higher ...

June 13, 2018 - Synopsys Design Platform Certified using 64-bit Arm Cortex-A53 Processor

Synopsys IC Validator Certified by Samsung Foundry for 7nm Signoff Physical ...

June 13, 2018 - IC Validator’s Massively Parallel Architecture and Samsung Foundry’s Runsets Accelerate Physical Signoff for Mutual Customers

FPGA Platform – Accelerate FPGA Design, Verification and Debug (Japanese)

Jun 6, 2018 - This webinar will detail how Synopsys solutions provide designers improvements in native integration, automation, runtime acceleration and technology advancements, to achieve the ...

ESP Bridging the Gap Video Serices

The videos in this series cover topics related to Synopsys ESP and formal verification for custom digital design. ESP is an equivalence checker for full custom designs that enables fast and ...

Synopsys Design Platform Certified for Samsung 8LPP Process Technology

May 22, 2018 - Silicon-proven Reference Flow Provides Quality-of-Results and Time-to-Results Advantage for High-performance, Low-power Applications

Signoff Leadership in Extending the Frontiers of Digital Design

Synopsys signoff solutions, including PrimeTime® and StarRC™, leading the industry with advanced innovation technologies that deliver golden accuracy, fast turnaround and best ...

Synopsys IC Validator Certified by GLOBALFOUNDRIES for Signoff Physical ...

May 14 - 14LPP Certification Enables High-Performance Physical Signoff for Mutual Customers

Fusion Technology: Broadly addressing the challenges of 5-nm-and-below processes

Architected to extract maximum process entitlement for 5-nm-and-beyond processes’, Synopsys’ latest Fusion Technology is helping customers realize optimal full-flow, power, performance and area ...

How to Reduce the Amount of Time to Fix DRCs Near Tapeout

In the later stages of design cycle, it is important to identify and fix DRC issues quickly to meet the tapeout schedule. This video discusses some techniques and best practices. Taking advantage ...