Chip Design Resources

Sort by

Synopsys Suggests

Effective and Robust SoC Connectivity Checks using TestMAX Advisor

Jul 8, 2020 - This webinar covers a collaborative effort between Intel and Synopsys resulting in the development and delivery of a comprehensive netlist DRC solution using TestMAX Advisor to ...

Synopsys and Arm Extend Strategic Partnership to Deliver Superior Full-Flow ...

Jun 29, 2020 - Multi-year Agreement Accelerates Design and Verification of Arm-based SoCs

Advanced Node Block Physical Signoff with IC Validator in Fusion Compiler

Jun 25, 2020 - In this webinar, learn how to use in-design physical verification to accelerate block signoff for advanced process nodes 7nm, 5nm and below.

Synopsys Awarded DARPA Contract for Automatic Implementation of Secure ...

Jun 25, 2020 - Advances SoC Design by Integrating Scalable Hardware Security Mechanisms Leveraging Academic and Commercial Partner Expertise, and Synopsys’ Industry-Leading EDA Platforms and IP

Samsung Foundry and Synopsys: Fast Accurate Silicon Diagnosis & Yield Analysis

Jun 24, 2020 - In this webinar learn the latest technology updates for silicon diagnostics and see examples of its application.

Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

Jun 23, 2020 - In this webinar, we review the glitch power challenges facing SoC designers and the key technologies that enable strong correlation between early glitch power analysis and final ...

Synopsys Collaboration with Samsung Foundry Enables Rollout of Samsung SAFE ...

Jun 17, 2020 - Cloud-scalable Synopsys Fusion Design, Custom Design, and Verification Continuum products available through the platform

Synopsys, TSMC and Microsoft Azure Deliver Highly Scalable Timing Signoff ...

Jun 15, 2020 - Major reduction in turnaround time for next-generation chips achieved through collaboration.

Addressing Functional Safety Issues Early and Cost Effectively

June 11, 2020 - This webinar will show how Synopsys TestMAX FuSa uses static analysis early in the design flow either at RTL or Gate netlist to calculate ISO 26262 metrics such as Single Point ...

Efficient Physical Verification for Silicon Photonics Designs

Jun 05, 2020 - This webinar discusses the advances in DRC and LVS verification to address the challenges for Photonics Integrated Circuits. We will cover new techniques in IC Validator to reliably ...