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Formality ECO: Functional ECOs Faster, Better, First Time Right!

Oct 22, 2020 - In this session, we will present the superiority of Formality ECO’s technology that delivers patches with minimal disturbance to the implemented design and enabling you to achieve ...

Ensuring Safety in Automotive IC Designs – TestMAX CustomFault

Sep 30, 2020 - In this Synopsys webinar we will describe the basics of analog fault simulation including how it can be used to model and verify the impact of random hardware failures in an IC, and ...

Case Study: Optimize and Configure Synopsys DesignWare IP with RTL Architect

Sep 29, 2020 - This webinar will provide a case study of how the Synopsys R&D team for DesignWare ARC EV Processor IP used RTL Architect to accelerate their IP’s time-to-market. It will explain how...

Synopsys and GLOBALFOUNDRIES Collaborate to Expand Fusion Compiler Benefits ...

Sep 24, 2020 - This collaboration will enable the fast-tracking of next-generation, market-shaping products in verticals such as aerospace and defense, automotive, data center, IoT and mobile on ...

Lowering Tapeout Risks with Advanced Technology to Overcome Today’s ECO ...

Sep 10, 2020 - As chip designs advance to lower process nodes, they have become more and more complex and power hungry. Every ECO change can potentially become a bottleneck and influence the tape ...

Best Verifiable QoR – A Formal Equivalence Checking Yardstick

Sep 8, 2020 - This presentation details how Formality Equivalence Checking gave Broadcom the confidence to verify and signoff designs without scaling back or switching off the optimizations or ...

Functional ECO Techniques for Faster Design Cycle Closure

Aug 26, 2020 - This webinar highlights functional ECO solutions and how they have helped in optimal patch generation and faster patch validation methods.

Synopsys and TSMC Accelerate 2.5D/3DIC Designs with ...

Aug 25, 2020 - Synopsys 3DIC Compiler platform reduces design turnaround time for chip-package co-design implementation.

Synopsys IC Validator, Running on AMD EPYC Processor Powered Azure Virtual ...

Aug 20, 2020 - IC Validator delivers 40 percent lower cost of ownership with optimal utilization of cloud.

StarRC Density Corner Value Proposition

StarRC Density corner feature can assist in reducing design TAT by using it at the block level of a hierarchical design. This video explains the block density feature of StarRC along with the value...