Chip Design Resources

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Synopsys Suggests

DFTMAX Compression Shared I/O

Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs

TSMC 2018 Open Innovation Platform Forum

Oct 3, 2018 - Visit Synopsys at the TSMC Open Innovation Platform Forum in Santa Clara

Graphcore Uses Synopsys Design Platform to Implement Colossus Chip to ...

Sep 18, 2018 - Synopsys Fusion Technology Enables Superior Power, Performance, Area for AI Chip Design

Cracking The Auto IC Market

Sep 6, 2018 - Race is on to grab a share of this growing market, but it’s not so simple.

Variation In Low-Power FinFET Designs

Oct 30, 2018 - Old solutions don’t necessarily work anymore, particularly at advanced nodes and ultra-low voltage.

Chip Aging Becomes Design Problem

Aug 09, 2018 - Assessing the reliability of a device requires adding more physical factors into the analysis, many of which are interconnected in complex ways

Changing the Design Flow

The rationale for fusing together various pieces of digital design.

More Sigmas in Auto Chips

Aug 02, 2018 - Increasing robustness levels will require significant changes throughout the entire automotive ecosystem.

Auto Chip Ecosystem Needs Common Language

Aug 02, 2018 - To reach the levels of robustness that autonomous vehicles will require, companies throughout the auto and semiconductor ecosystems are working with an eye toward high-sigma design.


The Certify prototyping software is a user-friendly tool that works directly from your RTL source code and ASIC IP.