Feb 3, 2021 - In this Synopsys webinar, we will discuss a novel solution for design robustness analysis and fixing in the face of escalating process and voltage variability at advanced nodes.
Dec 10, 2020 - In this webinar, we present an overview of AWRS, our recommended methodology for the use of sampling, including how to pick the right sample size, and present a set of guidelines ...
Dec 8, 2020 - This presentation describes the integration of Formality as an RTL-to-gates Formal Verification (FV) flow into ViaSat’s Lynx flow.
Dec 03, 2020 - Synopsys has collaborated with Samsung Foundry to deliver a fully qualified flow with significant gains in accuracy, turnaround time and designer productivity.
Dec 3, 2020 - In this Synopsys webinar, we will explore solutions to those challenges by demonstrating how to setup an IC Validator job and scale to thousands of CPU cores with EPYC servers on ...
Dec. 2, 2020 - Synopsys experts will present Fusion Compiler’s native, high-capacity, hierarchical-design capabilities and showcase a divide-and-conquer design methodology that delivers ...
Learn how ESP can solve your custom digital verification challenges.
Learn how the ESP device model technology can deliver speed and functional timing accuracy.
Learn how ESP’s powerful symbolic simulation technology can provide high functional verification coverage orders of magnitude faster than SPICE.
Nov 12, 2020 - Read about how process variability, physical effects, and the impact of interconnect are critical in timing analysis.