Chip Design Resources

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DFTMAX Compression Shared I/O

Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs

DFTMAX Ultra

Ultra-high Compression for Maximum Test Cost Reduction

Synopsys and Helic Deliver Unified Electromagnetic-Aware Analog and RF Custom...

Dec 14, 2017 - Helic Tools Integrated into Synopsys Custom Design Platform to Accelerate Robust Design

iC-Haus Selects Synopsys’ IC Validator and StarRC for Signoff

Dec 13, 2017 - IC Validator Physical Signoff and StarRC Extraction Signoff Displace Incumbent Tools

DecaWave Deploys Synopsys TetraMAX II ATPG on Latest Automotive Design to ...

Oct 31, 2017 - Company Standardizes on TetraMAX II Solution to Create Manufacturing Tests for All Designs

Synopsys Test Platform Tools Certified for the Most Stringent Level of ...

Oct 30, 2017 - Provides Highest Degree of Safety Related Confidence and Accelerates Functional Safety Qualification

Best Practices for FPGA Design Coding, Timing and Congestion Reduction

Oct 25, 2017 - This webinar provides tips on design coding, constraint definition, timing closure and how to reduce design congestion for faster turnaround times using Synplify

International Test Conference 2017

Test experts from leading companies describe how they are using the newest capabilities in Synopsys’ comprehensive test and yield solution

Samsung Certifies Synopsys Design Platform for 28nm FD-SOI Process Technology

Sep 24, 2017 - Reference Flow for Silicon-Proven Design Platform Accelerates Path to Lower Power and Design Cost

Synopsys Design Platform Certified by GLOBALFOUNDRIES for 22nm FD-SOI Process...

Sep 20, 2017 - Certification Enables Optimized Implementation and Predictable Signoff