Jul 31, 2019 - This webinar introduces the Identify® RTL debugger and its ability to instrument RTL HDL while still at the RT-Level and debug the implemented FPGA on live, running hardware.
July 16, 2019 - This webinar will provide an update on the latest design implementation technologies available in Synopsys’ IC Compiler II 2019.03.
Jul 11, 2019 - IC Validator Delivers Superior Performance for DRC and LVS Signoff
Jul 11, 2019 - Realtek Deploys IC Compiler II for Its Next-generation Communications Network Design
Jun 4, 2019 - AI-enhanced, Cloud-ready Platform with Fusion Technology Accelerates Next Wave of Industry Innovation
May 30, 2019 - Industry's First Full-chip Implementation and Verification Completed Entirely on Amazon Web Services Cloud
May 28, 2019 - Juniper Networks Achieves 14% Lower Power and 6% Smaller Area on Next-generation Networking Design
May 28, 2019 - Breakthrough Technology Redefines Design Signoff by Leveraging Industry's Golden Timing Signoff and Machine Learning Technology to Accelerate Statistical Yield Analysis
May 23, 2019 - Expanded Cloud-based Services Give SoC Designers More Scalability and Flexibility
May 20, 2019 - Complex interactions and power-related effects require understanding of how chips behave in context of real-world use cases.