Chip Design Resources

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Fast FPGA Debug for High Reliability and Functional Safety Designs

Jan 22, 2019 - This webinar introduces Synplify synthesis and its ability to quickly add triple modular redundancy (TMR) to a design.

Boosting Analog Reliability: Dealing with Variability and Physical Effects in...

Jan 17, 2019 - In this Tech Talk video with Semiconductor Engineering, Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid ...

AI's Growing Impact on Chip Design

Jan 16, 2019 - Semiconductor Engineering interviews Aart de Geus to discuss the impact of AI on chip design.

DFTMAX Compression Shared I/O

Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs

Physical Verification in the Cloud: IC Validator and AWS

Learn about IC Validator DRC on Amazon Web Services, scaling for faster performance, and elastic CPU management to add CPUs on the fly.

Toshiba Memory Corporation BiCS FLASH Memory

Synopsys speeds up verification and TTM of TMC BiCS FLASH memory

Ethernet PHY and Custom Compiler Workshop

Dec 7, 2018 - Hear from the Synopsys IP team about its high-speed 56G Ethernet PHY IP design project’s key findings, illustrating how designers can optimize their design methodology. Get hands-on ...

IC Validator Documentation

In this video, we will see where to find IC Validator related documentation and an overview of each.

IC Validator Text Options Function

The text_options() function specifies how layout text objects are processed as they are read in as a text layer. The function also specifies text options that apply to the entire runset. This ...

IC Validator Text Net Function

The text_net() function applies the specified text to the specified layers in the specified connect database. In this video, we will see an overview of IC Validator text_net() function.