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DFTMAX Compression Shared I/O

Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs

Ethernet PHY and Custom Compiler Workshop

Dec 7, 2018 - Hear from the Synopsys IP team about its high-speed 56G Ethernet PHY IP design project’s key findings, illustrating how designers can optimize their design methodology. Get hands-on ...

High Speed Ethernet PHY IP Design Methodology Optimization using Custom Compiler

Nov 20, 2018 - This webinar describes how the Synopsys Mixed-Signal IP team optimized their design methodology in a single custom design platform to meet the circuit design, simulations, layout and...

How to Execute Fill in IC Validator

Learn how to execute fill within IC Vaidator

How to compare LVS results using the DCV results compare tool

Learn how to compare LVS results using IC Validator DCV results compare tool (RCT). DCV RCT compares extraction stage results separately. You can use DCV RCT to compare only IC Validator LVS ...

How to Compare Two Netlists Using Netlist-Versus-Netlist in IC Validator

Learn how to compare two netlists of any format like SPICE, IC Validator or VERILOG using NVN utility. An Netlist-Versus-Netlist (NVN) flow varies from an LVS flow in that the NVN does not perform ...

Learn how to perform netlist translation and modification using IC Validator ...

NetTran is a netlist translation utility. NetTran translates a standard netlist format like SPICE, VERLOG to an IC Validator netlist format, or you can use IC Validator NetTran utility to merge ...

How to Run LVS Black Box Flow in IC Validator

LVS Black Box flow allows you to validate top-level designs before all of the building blocks in a top chip level are not completed. Any device data contained within the black box cell is ignored; ...

How to use Edtext files in IC Validator

Learn how to use Edtext file in IC Validator. An Edtext file consists list of text objects that are added to the specified cell on the specified layer number, data type and coordinates on the fly ...

How to Create an Equivalence File for an LVS Run

Learn how to create an equivalence file for LVS run. An equivalence file is used during LVS compare to list each schematic cell and the corresponding layout cell. IC Validator NetTran utility can ...