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Accelerated Optimization with IC Compiler II

Sep 2014 - Efficient optimization is a necessary yet challenging aspect of the physical implementation flow. Newer nodes and growing designs are all conspiring to place growing demands on this ...

Accelerating 20nm Double Patterning Verification

Oct 2012 - This whitepaper presents the key concepts of DPT compliant design and demonstrates how new signoff technology in IC Validator makes it possible to ensure 20nm manufacturing compliance

Accelerating Physical Verification Productivity for Advanced Node Designs ...

Mar 2019 - Learn how to increase productivity using IC Validator physical verification for advanced node designs.

Accelerating Toshiba's SoC Design with Fusion Compiler

Feb 2019 - Learn how Toshiba's early access to the industry’s only RTL-to-GDSII solution speeds time-to-market for their latest, advanced, automotive SoC

Accurate Signoff Using Path Based Analysis

Path-based analysis is a feature which was introduced in PrimeTime Y-2004.06 release. This technology offers a substantial improvement in static timing analysis accuracy for both PrimeTime and ...

Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill

May 2009 - Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays

Advanced Design Planning in IC Compiler II

Mar 2014 - Design exploration and planning is becoming an increasingly critical step of the design creation process as growing constraints and requirements are placed upon it. IC Compiler II has ...

Boosting Productivity by Using Look-ahead Constraint Analysis Technology

Aug 2010 - In this paper, we present a unique constraint analysis technology that checks for timing constraints problems and provides an interactive environment with context-sensitive diagnostic ...

Concurrent Clock and Data Optimization with IC Compiler II

Dec 2014 - To advance concurrent clock and data optimization, we need to go beyond incremental enhancements and bolt-on solutions. An optimal solution to CCD needs to provide a fast, convergent, ...

Custom and Mixed-Signal Design Solution

Synopsys’ unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of...