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DFTMAX Compression Shared I/O

Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs

Fusion Compiler Comprehensive RTL-to-GDSII Implementation System

Nov 2018 - The semiconductor industry is going through a renaissance period with waves of technological advancements and innovation...

Fusion Compiler Unified Physical Synthesis

Nov 2018 - Learn about the benefits of Fusion Compiler's unified optimization technologies that is enabling up to 20 percent improved performance, power and area (PPA ), while reducing ...

Synopsys Vision for the New Wave of Chip Design

Mar 2018 - Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm

Functional Safety for FPGA-Based Hardware Designs

Aug 2017 - Learn about the functional safety requirements defined by ISO 26262 for automotive and IEC 61508 for industrial applications that FPGA Designers are incorporating into their designs for ...

More Effective Test: Slack-Based Transition Delay

Jan 2017 - This white paper describes the basic principles related to SBTD, which is available in Synopsys’ synthesis-based test solution, DFTMAX and TetraMAX ATPG

The Path to (Virtually) Zero Defective Parts Per Million

Dec 2016 - Despite thorough wafer and package testing, a small number of defective ICs can make their way into systems. These test “escapes” often return as field failures, increasing costs and ...

Achieving ISO 26262 Software Tool Confidence for Improved Automotive ...

Nov 2016 - Achieving ISO 26262 Software Tool Confidence for Improved Automotive Functional Safety. The rapid adoption of advanced electronic systems in automobiles has prompted the automotive ...

Shift Left Your FPGA Design for Faster Time to Market

Oct 2016 - In just a few short years, FPGAs have become an integral part of system design for many applications either as a co-processor or the main system processor. As FPGA size and performance ...

Funktionssicherheit und verbesserte „Uptime“ durch TMR

Sep 2016 - Entwicklung zuverlässiger FPGA-Designs durch die Nutzung Von Triple-Modular-Redundancy (TMR). TMR erkennt und beseitigt Einzel-Bit-Fehler in Schaltkreisen durch das Einfügen von ...