Jul 31, 2019 - This webinar introduces the Identify® RTL debugger and its ability to instrument RTL HDL while still at the RT-Level and debug the implemented FPGA on live, running hardware.
July 16, 2019 - This webinar will provide an update on the latest design implementation technologies available in Synopsys’ IC Compiler II 2019.03.
Jan 22, 2019 - This webinar introduces Synplify synthesis and its ability to quickly add triple modular redundancy (TMR) to a design.
Nov 20, 2018 - This webinar describes how the Synopsys Mixed-Signal IP team optimized their design methodology in a single custom design platform to meet the circuit design, simulations, layout and...
Jun 6, 2018 - This webinar will detail how Synopsys solutions provide designers improvements in native integration, automation, runtime acceleration and technology advancements, to achieve the ...
Feb 13, 2018 - This webinar will detail how Synopsys solutions provide designers improvements in native integration, automation, runtime acceleration and technology advancements, to achieve the ...
Oct 25, 2017 - This webinar provides tips on design coding, constraint definition, timing closure and how to reduce design congestion for faster turnaround times using Synplify
Sep 14, 2017 - In this webinar, Meena Gupta will discuss how Cavium uses the latest technology in Design Compiler Graphical to achieve superior results while moving to an advanced process node.
Aug 23, 2017 - Renesas explains how they use Custom Compiler Co-Design with IC Compiler II in their production design environment to create high-quality shielded nets in in-vehicle CPU and IP modules
Jun 28, 2017 - Learn how to automatically “build-in” soft error detection and mitigation with Synopsys Synplify Premier FPGA design tools.