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FPGA Platform – Accelerate FPGA Design, Verification and Debug (Japanese)

Jun 6, 2018 - This webinar will detail how Synopsys solutions provide designers improvements in native integration, automation, runtime acceleration and technology advancements, to achieve the ...

Synopsys FPGA Platform - Enabling Planning to Synthesis

Feb 13, 2018 - This webinar will detail how Synopsys solutions provide designers improvements in native integration, automation, runtime acceleration and technology advancements, to achieve the ...

Best Practices for FPGA Design Coding, Timing and Congestion Reduction

Oct 25, 2017 - This webinar provides tips on design coding, constraint definition, timing closure and how to reduce design congestion for faster turnaround times using Synplify

Cavium Perspective: Achieving Optimal QoR Faster with Design Compiler Graphical

Sep 14, 2017 - In this webinar, Meena Gupta will discuss how Cavium uses the latest technology in Design Compiler Graphical to achieve superior results while moving to an advanced process node.

Renesas Case Study: Reducing Custom Net Routing Time by 4X for Automotive ...

Aug 23, 2017 - Renesas explains how they use Custom Compiler Co-Design with IC Compiler II in their production design environment to create high-quality shielded nets in in-vehicle CPU and IP modules

Accelerate FPGA Design Performance with Advanced Constraint Development ...

Jul 19, 2017 - Using Synplify Premier, learn how to setup a design, quickly find RTL compile errors, initially define constraints and tune the design for best performance.

Enabling Functional Safety for FPGA-based Hardware Design

Jun 28, 2017 - Learn how to automatically “build-in” soft error detection and mitigation with Synopsys Synplify Premier FPGA design tools.

Toshiba and Synopsys: Physically-aware Test Points to Improve ATPG and ...

May 18, 2017 - Learn how you can immediately use new test point technology in SpyGlass DFT ADV and DFTMAX to reduce ATPG patterns and boost BIST coverage.

Accelerate FPGA Design Performance and Advanced Constraint Development

Jan 25, 2017 - Using Synplify Premier, learn how to setup a design, quickly find RTL compile errors, initially define constraints and tune the design for best performance

PrimeTime User Case Studies: 5X Reduction in Hardware Cost with Reduced ...

Oct 26, 2016 - Design teams regularly face resource challenges as they near signoff and the number of scenarios being analyzed increases. In response to this, a new PrimeTime ECO technology has ...