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Formality ECO: Functional ECOs Faster, Better, First Time Right!

Oct 22, 2020 - In this session, we will present the superiority of Formality ECO’s technology that delivers patches with minimal disturbance to the implemented design and enabling you to achieve ...

Lowering Tapeout Risks with Advanced Technology to Overcome Today’s ECO ...

Sep 10, 2020 - As chip designs advance to lower process nodes, they have become more and more complex and power hungry. Every ECO change can potentially become a bottleneck and influence the tape ...

Best Verifiable QoR – A Formal Equivalence Checking Yardstick

Sep 8, 2020 - This presentation details how Formality Equivalence Checking gave Broadcom the confidence to verify and signoff designs without scaling back or switching off the optimizations or ...

Functional ECO Techniques for Faster Design Cycle Closure

Aug 26, 2020 - This webinar highlights functional ECO solutions and how they have helped in optimal patch generation and faster patch validation methods.

Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

Jun 23, 2020 - In this webinar, we review the glitch power challenges facing SoC designers and the key technologies that enable strong correlation between early glitch power analysis and final ...

Efficient Physical Verification for Silicon Photonics Designs

Jun 05, 2020 - This webinar discusses the advances in DRC and LVS verification to address the challenges for Photonics Integrated Circuits. We will cover new techniques in IC Validator to reliably ...

Static Timing Signoff and Model Generation for Complex Analog Mixed-Signal ...

May 13, 2020 - This webinar discusses a timing signoff methodology that uses transistor-level static timing analysis to augment dynamic simulation. This methodology performs validation for all ...

Advances in Timing Signoff to Address Today’s Design Challenges

May 5, 2020 - In this webinar, we will discuss major advances in timing signoff technologies that address the new challenges. We will cover new techniques to optimize timing accuracy and alleviate ...

Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk ...

Apr 9, 2020 - Watch this webinar to learn how to prevent and eliminate IR drop and power integrity issues using RedHawk Analysis Fusion.

Achieving Design Robustness in Signoff for Advanced Node Designs

Mar 26, 2020 - This webinar talks about some of the new techniques available from EDA tools such as StarRC to tackle advanced node hierarchical physical design challenges from an interconnect ...