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Validating Memory Design Scan Chains from Behavioral to Transistor Level

March 24, 2021 - In this Synopsys webinar, we will discuss the only solution for validating scan chains from higher behavioral models all the way down to transistor level implementation. By ...

Improve Design Robustness and Minimize Over-Pessimism in Face of Rising ...

Feb 3, 2021 - In this Synopsys webinar, we will discuss a novel solution for design robustness analysis and fixing in the face of escalating process and voltage variability at advanced nodes.

Deployment of Formality at ViaSat with Lynx Integration

Dec 8, 2020 - This presentation describes the integration of Formality as an RTL-to-gates Formal Verification (FV) flow into ViaSat’s Lynx flow.

Formality ECO: Functional ECOs Faster, Better, First Time Right!

Oct 22, 2020 - In this session, we will present the superiority of Formality ECO’s technology that delivers patches with minimal disturbance to the implemented design and enabling you to achieve ...

TSMC Timing Sign-Off in the Cloud with PrimeTime and StarRC

Oct 20, 2020 - This online event presents the collaboration among TSMC, Microsoft Azure, and Synopsys on how designers can successfully use PrimeTime and StarRC products to adopt Scale-Out and ...

Lowering Tapeout Risks with Advanced Technology to Overcome Today’s ECO ...

Sep 10, 2020 - As chip designs advance to lower process nodes, they have become more and more complex and power hungry. Every ECO change can potentially become a bottleneck and influence the tape ...

Best Verifiable QoR – A Formal Equivalence Checking Yardstick

Sep 8, 2020 - This presentation details how Formality Equivalence Checking gave Broadcom the confidence to verify and signoff designs without scaling back or switching off the optimizations or ...

Functional ECO Techniques for Faster Design Cycle Closure

Aug 26, 2020 - This webinar highlights functional ECO solutions and how they have helped in optimal patch generation and faster patch validation methods.

Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff

Jun 23, 2020 - In this webinar, we review the glitch power challenges facing SoC designers and the key technologies that enable strong correlation between early glitch power analysis and final ...

Efficient Physical Verification for Silicon Photonics Designs

Jun 05, 2020 - This webinar discusses the advances in DRC and LVS verification to address the challenges for Photonics Integrated Circuits. We will cover new techniques in IC Validator to reliably ...