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Advanced Node Block Physical Signoff with IC Validator in Fusion Compiler

Jun 25, 2020 - In this webinar, learn how to use in-design physical verification to accelerate block signoff for advanced process nodes 7nm, 5nm and below.

Efficient Physical Verification for Silicon Photonics Designs

Jun 05, 2020 - This webinar discusses the advances in DRC and LVS verification to address the challenges for Photonics Integrated Circuits. We will cover new techniques in IC Validator to reliably ...