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Synopsys Suggests

Boosting Analog Reliability: Dealing with Variability and Physical Effects in...

Jan 17, 2019 - In this Tech Talk video with Semiconductor Engineering, Synopsys' Aveek Sarkar talks about challenges with complex design rules, rigid design methodologies, and the gap between ...

Changing the Design Flow

The rationale for fusing together various pieces of digital design.

In-Design Power Rail Analysis

What can go wrong with power analysis at advanced nodes.

Tech Talk: 5/3nm Parasitics

What to expect at future process nodes

DAC 2017 Custom Compiler Lunch

Jun 20, 2017 - Cutting Custom Layout Tasks from Days to Hours

DAC 2018 Automotive Lunch

Jun 26, 2018 - Automotive Drives the Next Generation of Designs

DAC 2018 Custom Lunch

Jun 25, 2018 - Advancing Custom/AMS Design for Storage, Automotive, and AI Applications

Test SIG Dinner at ITC 2018

Oct 29, 2018 - Synopsys Customers are Invited to attend the 26th Annual Test SIG Event at ITC 2018 in Phoenix

SNUG 2017 Custom Compiler Lunch

Mar 23, 2017 - Cutting FinFET Layout Tasks from Days to Hours

SNUG 2017 Design Compiler Lunch

Mar 23, 2017 - Advanced Silicon Design Success with Design Compiler