Jan 17, 2019 - In this Tech Talk video with Semiconductor Engineering, Synopsys' Aveek Sarkar talks about challenges with complex design rules, rigid design methodologies, and the gap between ...
The rationale for fusing together various pieces of digital design.
What can go wrong with power analysis at advanced nodes.
What to expect at future process nodes
Technical tips for IC Validator, design rule checks, layout vs schematic, and hear customers experiences.
Jun 20, 2017 - Cutting Custom Layout Tasks from Days to Hours
Jun 26, 2018 - Automotive Drives the Next Generation of Designs
Jun 25, 2018 - Advancing Custom/AMS Design for Storage, Automotive, and AI Applications
Sep 14, 2016 - High-performance Design Success with IC Compiler II
Oct 29, 2018 - Synopsys Customers are Invited to attend the 26th Annual Test SIG Event at ITC 2018 in Phoenix