Chip Design Resources

Sort by

Synopsys Suggests

DAC 2017 Custom Compiler Luncheon Videolog

Cutting custom layout tasks from days to hours

SNUG Silicon Valley 2017 Design Compiler Lunch 'n' Learn

Advanced silicon design success with Design Compiler

SNUG Silicon Valley 2017 Custom Compiler Lunch 'n' Learn

Cutting FinFET layout tasks from days to hours

Smarter Library Voltage Scaling with PrimeTime

Designs outside of library voltage corners supplied by the foundry can require expensive and time consuming effort to obtain the correct library. Eliminating the need for a library for each ...

Test SIG Event at ITC 2016

In these videos, recorded out the 24th Annual Test SIG Event at ITC 2016, Test experts Toshiba, Bosch and STMicroelectronics describe how they are using the newest capabilities in Synopsys’ ...

International Test Conference 2016

Test experts Broadcom, STMicroelectronics and Toshiba describe how they are using newest capabilities in Synopsys comprehensive test and yield solution

Arm TechCon 2016: HiSilicon Collaboration

Learn about Arm, Synopsys and HiSilicon collaboration

SNUG India 2016 Test Panel

Learn about ATPG solution TetraMax II from Test experts from Broadcom, STMicroelectronics and Toshiba

Introduction to TetraMAX II

Antun Domic, Executive VP and GM of the Design Group unveils Synopsys' next-generation ATPG and diagnostics solution. TetraMAX II surpasses previous technologies that are limited by high memory ...