Chip Design Resources

Sort by

Synopsys Suggests

Fusion Compiler Deployment - The Journey So Far

Raghavendra Swami Sadhu from Samsung India summarizes recent challenges of high-performance, full-chip SoCs. He highlighted Fusion Compiler’s high capacity and production-ready R2G flow with DFT ...

Custom Compiler Visually-Assisted Automation

Graphical Guidance and Real-time Visual Feedback

Golden Signoff Embedded in the RTL-to-GDSII Design Flow with Fusion Compiler

Dr. Henry Sheng, group director of R&D at Synopsys, discusses how Fusion Compiler delivers signoff-accurate PPA on high-performance, low-power designs at advanced nodes, and accelerates design ...

CCD Everywhere Throughout the RTL-to-GDSII Design Flow with Synopsys’ Fusion ...

Dr. Aiqun Cao, VP of Engineering for Synopsys’ Design Group, discusses how Fusion Compiler’s unified physical synthesis and common optimization framework enables full-flow concurrent clock and data...

Fusion: The Vision, the Ethos and the Bold Bet Reshaping Digital Design

Aart De Geus, Co-CEO of Synopsys, discusses the ethos of the Fusion concept at the heart of Synopsys’ Fusion Design Platform, how Fusion Compiler was born of this vision and how, in one year, it is...

Bold, Different and Smarter: How Synopsys is Innovating to Keep You Ahead of ...

Sassine Ghazi, GM of Synopsys’ Design Group, discusses how a revolution in digital design was started by creating a single data model for all design, and he describes how Fusion Compiler, the ...

Broadcom Discuss Experience Using Formality for Interactive ECO Implementation

At Silicon Valley SNUG 2019, Broadcom presented a paper on their success implementing manual ECO’s with Formality’s interactive ECO functionality. Listen to Sathappan Palaniappan, Principal ...

SNUG 2019 Custom Design Platform Lunch

Mar 21, 2019 - Learn about accelerating robust custom design from Arm, Samsung, STMicroelectronics and Synopsys in this SNUG Lunch and Learn event recording.

SNUG Silicon Valley 2019 Test Lunch Panel

At SNUG Silicon Valley 2019, Synopsys TestMAX was unveiled during a special lunch event with a panel of test experts. Watch the videos to learn more.

Innovations in IC Validator for Advanced Node Physical Signoff

Learn about the latest technologies in IC Validator including; Explorer, Live, Scalability, Elastic Computing and more. Shorten time to tapeout by 2x.