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nnovations in IC Validator for Advanced Node Physical Signoff

Learn about the latest technologies in IC Validator including; Explorer, Live, Scalability, Elastic Computing and more. Shorten time to tapeout by 2x.

On-demand Signoff DRC Checking for Custom Design Flows

Designers need immediate and on-the-fly DRC feedback as they do the layout edits. IC Validator Live DRC checking offers signoff quality DRC checking directly.

IC Validator DRC Checking

How to Accelerate DRC Checking During SoC Integration

Boosting Analog Reliability: Dealing with Variability and Physical Effects in...

Jan 17, 2019 - In this Tech Talk video with Semiconductor Engineering, Synopsys' Aveek Sarkar talks about challenges with complex design rules, rigid design methodologies, and the gap between ...

Physical Verification in the Cloud: IC Validator and AWS

Learn about IC Validator DRC on Amazon Web Services, scaling for faster performance, and elastic CPU management to add CPUs on the fly.

Toshiba Memory Corporation BiCS FLASH Memory

Synopsys speeds up verification and TTM of TMC BiCS FLASH memory

IC Validator Documentation

In this video, we will see where to find IC Validator related documentation and an overview of each.

IC Validator Text Options Function

The text_options() function specifies how layout text objects are processed as they are read in as a text layer. The function also specifies text options that apply to the entire runset. This ...

IC Validator Text Net Function

The text_net() function applies the specified text to the specified layers in the specified connect database. In this video, we will see an overview of IC Validator text_net() function.

IC Validator Hierarchy Options Function

The hierarchy_options() function in a runset modifies the hierarchy in the input layout design. In this video, we will see an overview of IC Validator hierarchy_options() function.