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AI Hardware Summit Video

Sept. 18, 2018 - Enabling Device Intelligence—AI Chip Design from the Data Center to the Edge

Changing the Design Flow

The rationale for fusing together various pieces of digital design.

In-Design Power Rail Analysis

What can go wrong with power analysis at advanced nodes.

DAC 2018 Automotive Lunch

Jun 26, 2018 - Automotive Drives the Next Generation of Designs

DAC 2018 Custom Lunch

Jun 25, 2018 - Advancing Custom/AMS Design for Storage, Automotive, and AI Applications

Signoff Leadership in Extending the Frontiers of Digital Design

Synopsys innovative advanced signoff solutions deliver golden accuracy, fast turnaround and best power-performance-area to push IC design to new frontiers.

ECO Fusion Delivering Best QoR and Fastest Time to Results to STMicroelectronics

ST Microelectronics shares how ECO Fusion enables signoff analysis within IC Compiler II, saving time and increasing accuracy.

Toshiba Discusses Using RedHawk Analysis Fusion in IC Complier II

Learn about Toshiba's experience using in-Design rail analysis flow with RedHawk Analysis Fusion

Fusion Technology: Broadly addressing the challenges of 5-nm-and-below processes

Architected to extract maximum process entitlement for 5-nm-and-beyond processes’, Synopsys’ latest Fusion Technology is helping customers realize optimal full-flow, power, performance and area ...

How to Reduce the Amount of Time to Fix DRCs Near Tapeout

In the later stages of design cycle, it is important to identify and fix DRC issues quickly to meet the tapeout schedule. This video discusses some techniques and best practices. Taking advantage ...