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Synopsys Suggests

DFTMAX Compression Shared I/O

Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs

Synopsys Vision for the New Wave of Chip Design

Mar 2018 - Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm

More Effective Test: Slack-Based Transition Delay

Jan 2017 - This white paper describes the basic principles related to SBTD, which is available in Synopsys’ synthesis-based test solution, DFTMAX and TetraMAX ATPG

The Path to (Virtually) Zero Defective Parts Per Million

Dec 2016 - Despite thorough wafer and package testing, a small number of defective ICs can make their way into systems. These test “escapes” often return as field failures, increasing costs and ...

Low DPPM Testing for Advanced Process Nodes and FinFETs

Feb 2014 - At advanced nodes, process variations give rise to physical defects that require additional tests for achieving low defective parts per million (DPPM). This paper highlights low DPPM ...

Introducing DFTMAX Ultra: New Technology to Address Key Test Challenges

Sep 2013 - This paper explains how DFTMAX Ultra delivers new scan compression technology that further reduces test cost and simplifies design impact, providing improvements in test quality

Test Automation of 3D Integrated Systems

Jan 2012 - This whitepaper discusses some of the key challenges related to testing 3D integrated systems, and how early adopters can use Synopsys' synthesis-based test solution to maximize their ...

Synthesis-Based Test For Maximum RTL Designer Productivity

Oct 2010 - Exponential growth in size and complexity of systems on a chip (SoCs), coupled with increasingly stringent quality mandates, necessitates an efficient and productive approach for ...

Testing Low Power Designs with Power Aware Test

Apr 2010 - The most important trend over the past decade for semiconductor design is the dominant requirement to reduce power consumption and power dissipation. Not only do competitive products ...

Using TetraMAX® Physical Diagnostics for Advanced Yield Analysis

Jan 2010 - Scan-based DFT is now the standard digital logic testing used on almost all SoC designs.