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Fusion Compiler Unified Physical Synthesis

Nov 2018 - Learn about the benefits of Fusion Compiler's unified optimization technologies that is enabling up to 20 percent improved performance, power and area (PPA ), while reducing ...

Synopsys Vision for the New Wave of Chip Design

Mar 2018 - Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm

Debugging Non-equivalent Designs Using Formality

It is important to have a basic understanding of how to investigate verification failures in order to get things back on track as quickly as possible. Using debugging tools becomes very important ...

ECO Implementation and Verification Using Formality Ultra

Formality Ultra is an extension to the Formality equivalence-checking solution. This article describes how Formality Ultra can be used to aid in the analysis, modification, and verification of a ...

Boosting Productivity by Using Look-ahead Constraint Analysis Technology

Aug 2010 - In this paper, we present a unique constraint analysis technology that checks for timing constraints problems and provides an interactive environment with context-sensitive diagnostic ...

Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill

May 2009 - Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays

PrimeTime Mode Merging – Reducing Analysis cost for Multimode Designs

Oct 2013 - As process technologies shrink, design teams can fit increasing amounts of logic in a single chip, combining functionality that was captured in the past by discrete devices

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Feb 2014 - This paper explains how the timing ECO flow delivers fast, predictable, signoff-driven timing closure in a single pass

StarRC™ Custom: Next-Generation Modeling and Extraction Solution for Custom ...

May 2010 - Custom digital, analog/mixed-signal, and memory designs are particularly sensitive to the nanometer device parameters and parasitics

Benefits of Using ESP in Memory Designs

ESP is an equivalence checking tool commonly used for full functional verification of custom designs such as memories, custom macros, standard cell, and IO cell libraries. It is used to ensure that...