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Fusion Compiler Unified Physical Synthesis

Nov 2018 - Learn about the benefits of Fusion Compiler's unified optimization technologies that is enabling up to 20 percent improved performance, power and area (PPA ), while reducing ...

Synopsys Vision for the New Wave of Chip Design

Mar 2018 - Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm

Compare Point Matching

An important step in using combinational equivalence checkers to verify sequential designs is identifying and matching corresponding compare-points in the two sequential designs to be verified. - ...

Debugging Non-equivalent Designs Using Formality

It is important to have a basic understanding of how to investigate verification failures in order to get things back on track as quickly as possible. Using debugging tools becomes very important ...

Formality Equivalence Checker

This paper discusses the available methodologies for verifying arithmetic designs, the strengths and weaknesses of available approaches, and Formality's new methodology to greatly improve the ...

Formality Error-ID Technology Defines Debug Productivity

Have you ever experienced the "now what" anxiety that accompanies a failing equivalence checking verification? Have you found yourself staring at a logic cone with thousands of gates and no clear ...

A Safe Approach to Hierarchical UPF Verification in Formality

The IEEE-1801 IEEE Standard for Design and Verification of LowPower Integrated Circuits (UPF) adds additional constraints on the design affecting synthesis and verification. Using Formality with ...

ECO Implementation and Verification Using Formality Ultra

Formality Ultra is an extension to the Formality equivalence-checking solution. This article describes how Formality Ultra can be used to aid in the analysis, modification, and verification of a ...

Guidance Simplifies Equivalence Checking

It can be very challenging to functionally verify a design that has undergone significant transformations during implementation. This paper discusses the use of setup guidance to simplify the ...

Hier-IQ Fact Sheet

Today’s complex SoC designs present many verification challenges for design teams. Historically, to ensure design integrity throughout the implementation process, engineers used a bottom-up, ...