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Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill

May 2009 - Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays

Benefits of Using ESP in Memory Designs

ESP is an equivalence checking tool commonly used for full functional verification of custom designs such as memories, custom macros, standard cell, and IO cell libraries. It is used to ensure that...

Boosting Productivity by Using Look-ahead Constraint Analysis Technology

Aug 2010 - In this paper, we present a unique constraint analysis technology that checks for timing constraints problems and provides an interactive environment with context-sensitive diagnostic ...

Debugging Non-equivalent Designs Using Formality

It is important to have a basic understanding of how to investigate verification failures in order to get things back on track as quickly as possible. Using debugging tools becomes very important ...

Fusion Compiler Unified Physical Synthesis

Nov 2018 - Learn about the benefits of Fusion Compiler's unified optimization technologies that is enabling up to 20 percent improved performance, power and area (PPA ), while reducing ...

Lower Process Nodes Drive Timing Signoff Software Evolution

Oct 2020 - In this whitepaper, we will describe major advances in timing signoff technologies that address the new challenges.

PrimeTime Mode Merging – Reducing Analysis cost for Multimode Designs

Oct 2013 - As process technologies shrink, design teams can fit increasing amounts of logic in a single chip, combining functionality that was captured in the past by discrete devices

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Feb 2014 - This paper explains how the timing ECO flow delivers fast, predictable, signoff-driven timing closure in a single pass

StarRC Custom Rapid3D Extraction

Jun 01, 2010 - The next-generation Rapid3D technology in StarRC Custom provides an integrated 3D extraction solution to address these growing accuracy, performance, capacity and ease-of-use needs. ...

StarRCâ„¢ Custom: Next-Generation Modeling and Extraction Solution for Custom ...

May 2010 - Custom digital, analog/mixed-signal, and memory designs are particularly sensitive to the nanometer device parameters and parasitics