Chip Design Resources

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Synopsys Suggests

Changing the Design Flow

The rationale for fusing together various pieces of digital design.

Tech Talk: 5/3nm Parasitics

What to expect at future process nodes

The Choice of Transistor Architecture for the 5-nm Node and Beyond

Learn about the most likely options for transistor architectures as we move beyond the 5-nm node and how this is demanding a broader solution of “variability-driven engineering”.

Accurate and Timely Status Reports Using Lynx Design System Design Tracker

Learn about how Lynx Design System’s Design Tracker enables quick access to project status and reports to facilitate data-driven decisions.

Innovation Through Technology Leadership and Partnership-Oriented DNA

The most advanced volume production nodes are 12/10 nanometers, while 8/7 nanometers, both immersion lithography and EUV, are in final stages of development, and will move into volume production soon.

AI Hardware Summit Video

Sept. 18, 2018 - Enabling Device Intelligence—AI Chip Design from the Data Center to the Edge

Platform-Wide Innovations to Meet the Challenges of 5-nm and Beyond

With the advent of 5nm and the need for best in class power, performance, and area requirements there is an unprecedented need for integration across synthesis, place and route, and signoff. ...

Better Modeling of Clock Net Inductance for 7 and 5 Nanometer Designs

Inductance effects on clock nets can have serious consequences to performance and reliability of today’s advanced process technology designs. In this video, Greg Rollins, principle engineer from ...

ECO Fusion Delivering Best QoR and Fastest Time to Results to STMicroelectronics

ST Microelectronics shares how ECO Fusion enables signoff analysis within IC Compiler II, saving time and increasing accuracy.

Fusion Design Platform Technical Overview

Shankar Krishnmoorthy discusses the historical legacy and how we have continuously evolved with the ever-present challenges to deliver best-in-class synthesis solutions.