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Fusion Design Platform Technical Overview

Shankar Krishnmoorthy discusses the historical legacy and how we have continuously evolved with the ever-present challenges to deliver best-in-class synthesis solutions.

Fusion Compiler Complete RTL-to-GDSII System with Integrated Signoff-quality ...

Learn about how Fusion Compiler's integrated signoff-quality engines enables designers to achieve the highest performance, lowest power and area on their SoC designs.

Introducing the Next Evolution of Synopsys' Digital Toolset

Announcing a new era in digital implementation with Fusion Compiler and Design Compiler NXT at the center of the next generation of Synopsys digital design.

Fusion Design Platform

Introducing the latest full-flow RTL-to-GDSII platform solution from Synopsys. Built using market leading point tools and unique Fusion Technologies.

AI Hardware Summit Video

Sept. 18, 2018 - Enabling Device Intelligence—AI Chip Design from the Data Center to the Edge

Changing the Design Flow

The rationale for fusing together various pieces of digital design.

Signoff Leadership in Extending the Frontiers of Digital Design

Synopsys innovative advanced signoff solutions deliver golden accuracy, fast turnaround and best power-performance-area to push IC design to new frontiers.

ECO Fusion Delivering Best QoR and Fastest Time to Results to STMicroelectronics

ST Microelectronics shares how ECO Fusion enables signoff analysis within IC Compiler II, saving time and increasing accuracy.

Toshiba Discusses Using RedHawk Analysis Fusion in IC Complier II

Learn about Toshiba's experience using in-Design rail analysis flow with RedHawk Analysis Fusion

Better Modeling of Clock Net Inductance for 7 and 5 Nanometer Designs

Inductance effects on clock nets can have serious consequences to performance and reliability of today’s advanced process technology designs. In this video, Greg Rollins, principle engineer from ...