Chip Design Resources

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Synopsys Suggests

ESP

Custom Design Formal Equivalence Checking Based on Symbolic Simulation

Formality and Formality Ultra

Equivalence Checking for DC Ultra and Design Compiler Graphical

NanoTime

Transistor-level Static Timing Analysis Solution for Custom Design

PrimeRail

In-Design Rail Analysis for Place-and-Route Engineers

PrimeTime

Golden Timing Signoff STA Solution and Environment

QuickCap NX

3D Field Solver For 14nm FinFET and Beyond Process Technologies

SiliconSmart

Comprehensive Cell, I/O and Memory Characterization

StarRC

Parasitic Extraction for Digital and Custom Design