Chip Design Resources

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7/5nm Timing Closure Intensifies

Jan 25, 2018 - The issues may be familiar, but they’re more difficult to solve and can affect everything from performance to yield.

Chip Aging Accelerates

Feb 14, 2018 - As advanced-node chips are added into cars, and usage models shift inside of data centers, new questions surface about reliability.

Functional Safety Implementation Goes Mainstream

Oct 22, 2019 - In order to be compliant with ISO 26262 requirements, companies need to perform a software tool qualification assessment of the EDA tools they use to establish that the design tool ...

Fusion Improves Timing Say Synopsys Users

Jul 03, 2018 - Early-access customers talk about their experiences using Fusion Technology enabled portfolio of tools at DAC 2018.

Getting Better Results Faster with a Unified RTL-to-GDSII Product

Sep 3, 2019 - Advanced process nodes require new design tools. A single RTL-to-GDSII solution with a unified data model brings better results faster – by design.

Is 5 nm Testing the Same or Different

Apr 11, 2018 - What test methodologies and technologies must be applied to detect all manufacturing defects present in new process nodes such as 5 nm and beyond? If not captured at silicon test ...

No More PIzza! Bringing Power to the Age-old Question: "What's for Dinner?"

Sep 26, 2019 How high-performance computing affects simple decisions like what to have for dinner.

Regain Your Power With Machine Learning

Feb 22, 2018 - How machine learning can help meet PPA challenges and improve ECO optimization productivity

Synopsys Integrates Helic’s EM Tools to Tighten Margins on Mixed-signal, ...

Jan 5, 2018 - Synopsys and Helic have integrated Helic's VeloceRF RF device synthesis, RaptorX electromagnetic (EM) modeling and Exalto EM parasitic extraction and sign-off tools with Synopsys' ...

Synopsys Speeds PrimeTime with AI

Jun 06, 2018 - Synopsys is bringing artifical intelligence to it's PrimeTime signoff tool.