Chip Design Resources

Sort by

Synopsys Suggests

AI Hardware Demands the Highest Verificable QoR

Dec 09, 2019 - To help drive better PPA results, some EDA tools have implemented specific AI-oriented optimizations that take place throughout the RTL-to-GDSII flow from synthesis to implementation.

No More PIzza! Bringing Power to the Age-old Question: "What's for Dinner?"

Sep 26, 2019 How high-performance computing affects simple decisions like what to have for dinner.

Getting Better Results Faster with a Unified RTL-to-GDSII Product

Sep 03, 2019 - Advanced process nodes require new design tools. A single RTL-to-GDSII solution with a unified data model brings better results faster – by design.

Fusion Improves Timing Say Synopsys Users

Jul 03, 2018 - Early-access customers talk about their experiences using Fusion Technology enabled portfolio of tools at DAC 2018.

Enabling Simply Better RTL

Vineet Rashingkar, R&D Director at Synopsys