Chip Design Resources

Sort by

Synopsys Suggests

Debugging Point-to-Point Resistance Using Contribution by Layer in IC ...

June 2021 - Learn how IC Validator™ PERC includes all the needed capabilities for a point-to-point (P2P) resistance flow.

Optimize Physical Verification Cost of Ownership with Elastic CPU Management

May 2021 - Learn how IC Validator elastic CPU management technology delivers significant value in the design flow both in resource/cost optimization and in accelerating design closure to meet ...

Machine Learning — Everywhere: Enabling Self-Optimizing Design Platforms for ...

Jul 2020 - Machine-learning offers opportunities to enable self-optimizing design tools. AI-enhanced tools are able to learn and improve in (local) design environments after deployment.

Accelerating Physical Verification Productivity for Advanced Node Designs ...

Mar 2019 - Learn how to increase productivity using IC Validator physical verification for advanced node designs.

IC Validator Programmable EERC Mixed Mode Checking Technology

Jun 2016 - A new, comprehensive reliability solution is needed to reduce time to market, improve reliability and ensure longer device operation. This paper is a companion to the introductory IC ...

IC Validator and In-Design Metal Fill in IC Compiler II

Nov 2015 - Metal fill has evolved from an afterthought performed by the foundries to a mission critical design requirement that customers now carefully design themselves in order to achieve high ...

FinFET Technology – Understanding and Productizing a New Transistor From TSMC...

Apr 2013 - This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution.

Physical Verification of FinFETs and Fully Depleted SOI

Nov 2012 - It has come to be broadly accepted in the semiconductor industry that short-channel effects severely limit bulk planar transistor performance, and alternative device structures will ...

Accelerating 20nm Double Patterning Verification

Oct 2012 - This whitepaper presents the key concepts of DPT compliant design and demonstrates how new signoff technology in IC Validator makes it possible to ensure 20nm manufacturing compliance

IC Validator: GDS Merge

Sep 2010 - This paper presents an optimal approach to creating a working snapshot of a design’s complete mask data set for the purposes of in-design physical verification with IC Validator.