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Synopsys Vision for the New Wave of Chip Design

Mar 2018 - Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm

IC Validator Programmable EERC Mixed Mode Checking Technology

Jun 2016 - A new, comprehensive reliability solution is needed to reduce time to market, improve reliability and ensure longer device operation. This paper is a companion to the introductory IC ...

IC Validator and In-Design Metal Fill in IC Compiler II

Nov 2015 - Metal fill has evolved from an afterthought performed by the foundries to a mission critical design requirement that customers now carefully design themselves in order to achieve high ...

FinFET Technology – Understanding and Productizing a New Transistor From TSMC...

Apr 2013 - This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution.

Physical Verification of FinFETs and Fully Depleted SOI

Nov 2012 - It has come to be broadly accepted in the semiconductor industry that short-channel effects severely limit bulk planar transistor performance, and alternative device structures will ...

Accelerating 20nm Double Patterning Verification

Oct 2012 - This whitepaper presents the key concepts of DPT compliant design and demonstrates how new signoff technology in IC Validator makes it possible to ensure 20nm manufacturing compliance

IC Validator: GDS Merge

Sep 2010 - This paper presents an optimal approach to creating a working snapshot of a design’s complete mask data set for the purposes of in-design physical verification with IC Validator.

In-Design Rail Analysis™ Accelerates Power Network Closure

Sep 2009 - Complex system-on-chip (SoC) designs, static and dynamic voltage-drop and electromigration (EM) effects are increasing. At 90 nanometer (nm) and below, these effects are having a ...

Accelerating Physical Verification with an In-Design Flow

May 2009 - There is a growing need for a concurrent physical design and physical verification flow, also known as an in-design physical verification flow. This flow improves the overall turnaround ...

Enhancing the DRC Waiver Methodology for Layout Verification Productivity

May 2009 - To manage design violations, CAD departments have employed a number of solutions to reduce the amount of violations needed to be checked by the physical verification engineer