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Fusion Compiler Comprehensive RTL-to-GDSII Implementation System

Nov 2018 - The semiconductor industry is going through a renaissance period with waves of technological advancements and innovation...

Fusion Compiler Unified Physical Synthesis

Nov 2018 - Learn about the benefits of Fusion Compiler's unified optimization technologies that is enabling up to 20 percent improved performance, power and area (PPA ), while reducing ...

Synopsys Vision for the New Wave of Chip Design

Mar 2018 - Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm

IC Validator Programmable EERC Netlist Domain Checking Technology

Jun 2016 - Traditional visual inspection or manual checking for electrical rule compliance is both time consuming and error prone. A new, comprehensive reliability solution is needed to reduce time...

IC Compiler II Multi-Level Physical Hierarchy Floorplanning

Jan 2016 - Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a ...

IC Validator and In-Design Metal Fill in IC Compiler II

Nov 2015 - Metal fill has evolved from an afterthought performed by the foundries to a mission critical design requirement that customers now carefully design themselves in order to achieve high ...

Concurrent Clock and Data Optimization with IC Compiler II

Dec 2014 - To advance concurrent clock and data optimization, we need to go beyond incremental enhancements and bolt-on solutions. An optimal solution to CCD needs to provide a fast, convergent, ...

IC Compiler II: 5X Faster Closure on Advanced Designs With Complex MCMM

Dec 2014 - IC Compiler II with its native support for MCMM and MV is the most comprehensive, physical implementation system for advanced designs. It delivers 5X faster throughput, 3X larger ...

IC Compiler II: Finding the Best Floorplan, Fast

Nov 2014 - Today’s designs are large and very complex, requiring hierarchical planning and implementation methodologies. A fast, accurate solution enables design teams to converge on the best ...

Accelerated Optimization with IC Compiler II

Sep 2014 - Efficient optimization is a necessary yet challenging aspect of the physical implementation flow. Newer nodes and growing designs are all conspiring to place growing demands on this ...