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Enabling Arm’s Highest-Performance CPU Core Design

Haroon Gauhar of Arm outlines the design challenges of high-performance cores, where fast RTL feedback and skew optimization are decisive factors of reaching best frequency. He highlights Fusion ...

Superior Reliability for Automotive Designs

Satoshi Shibatani of Renesas Electronics Corporation explains the unique reliability requirements of automotive MCUs and SoCs. He highlights how the native FuSa support in Fusion Compiler improved ...

Fusion Compiler Deployment - The Journey So Far

Raghavendra Swami Sadhu from Samsung India summarizes recent challenges of high-performance, full-chip SoCs. He highlighted Fusion Compiler’s high capacity and production-ready R2G flow with DFT ...

Golden Signoff Embedded in the RTL-to-GDSII Design Flow with Fusion Compiler

Dr. Henry Sheng, group director of R&D at Synopsys, discusses how Fusion Compiler delivers signoff-accurate PPA on high-performance, low-power designs at advanced nodes, and accelerates design ...

CCD Everywhere Throughout the RTL-to-GDSII Design Flow with Synopsys’ Fusion ...

Dr. Aiqun Cao, VP of Engineering for Synopsys’ Design Group, discusses how Fusion Compiler’s unified physical synthesis and common optimization framework enables full-flow concurrent clock and data...

Fusion: The Vision, the Ethos and the Bold Bet Reshaping Digital Design

Aart De Geus, Co-CEO of Synopsys, discusses the ethos of the Fusion concept at the heart of Synopsys’ Fusion Design Platform, how Fusion Compiler was born of this vision and how, in one year, it is...

Bold, Different and Smarter: How Synopsys is Innovating to Keep You Ahead of ...

Sassine Ghazi, GM of Synopsys’ Design Group, discusses how a revolution in digital design was started by creating a single data model for all design, and he describes how Fusion Compiler, the ...

Broadcom Discuss Experience Using Formality for Interactive ECO Implementation

At Silicon Valley SNUG 2019, Broadcom presented a paper on their success implementing manual ECO’s with Formality’s interactive ECO functionality. Listen to Sathappan Palaniappan, Principal ...

Unveiling Innovations for Digital Design

Dr. Aart de Geus describes the dynamics that are driving the need for the fusion of synthesis and place-and-route technologies to achieve best PPA and predictable design closure, enabling the ...

Select/Unselect DRC Rule Checks for IC Validator Run

Learn how to run Design Rule Checks (DRC) interactively from IC Validator VUE interface. IC Validator VUE is a flow based graphical tool that guides you through the entire physical verification ...