At Silicon Valley SNUG 2019, Broadcom presented a paper on their success implementing manual ECO’s with Formality’s interactive ECO functionality. Listen to Sathappan Palaniappan, Principal ...
Dr. Aart de Geus describes the dynamics that are driving the need for the fusion of synthesis and place-and-route technologies to achieve best PPA and predictable design closure, enabling the ...
Shankar Krishnmoorthy discusses the historical legacy and how we have continuously evolved with the ever-present challenges to deliver best-in-class synthesis solutions.
Learn how to run Design Rule Checks (DRC) interactively from IC Validator VUE interface. IC Validator VUE is a flow based graphical tool that guides you through the entire physical verification ...
Learn about the benefits of Fusion Compiler built on a compact, single data model that enables seamless sharing of technology and engines for comprehensive design closure.
Learn about how Fusion Compiler's integrated signoff-quality engines enables designers to achieve the highest performance, lowest power and area on their SoC designs.
Transforming how designers go from RTL to placement in a single design cockpit.
The first RTL-to-GDSII, synthesis and place-and-route solution, enabling highly-convergent and predictable digital implementation.
Announcing a new era in digital implementation with Fusion Compiler and Design Compiler NXT at the center of the next generation of Synopsys digital design.
Introducing the latest full-flow RTL-to-GDSII platform solution from Synopsys. Built using market leading point tools and unique Fusion Technologies.