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Enabling Faster Time to First Prototype using FPGA Synthesis Tools

May 18, 2021 - Learn how to complete a gated clock conversion, enable DesignWare IP within an FPGA prototyping project, and how to include power management intent in an FPGA prototype.

Verifying Functional Safety Designs with Fault Simulation

Apr 14, 2020 - This webinar presents a methodology to effectively verify the functional safety logic implemented by Synplify Premier at the early stages of the design flow using fault ...

Fast FPGA Design Debug using Integrated Platform Solution

Jul 31, 2019 - This webinar introduces the Identify® RTL debugger and its ability to instrument RTL HDL while still at the RT-Level and debug the implemented FPGA on live, running hardware.

Fast FPGA Debug for High Reliability and Functional Safety Designs

Jan 22, 2019 - This webinar introduces Synplify synthesis and its ability to quickly add triple modular redundancy (TMR) to a design.

Synopsys FPGA Platform - Enabling Planning to Synthesis

Feb 13, 2018 - This webinar will detail how Synopsys solutions provide designers improvements in native integration, automation, runtime acceleration and technology advancements, to achieve the ...

Enabling Functional Safety for FPGA-based Hardware Design

Jun 28, 2017 - Learn how to automatically “build-in” soft error detection and mitigation with Synopsys Synplify Premier FPGA design tools.