Chip Design Resources

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Fast FPGA Design Debug using Integrated Platform Solution

Jul 31, 2019 - This webinar introduces the Identify® RTL debugger and its ability to instrument RTL HDL while still at the RT-Level and debug the implemented FPGA on live, running hardware.

Fast FPGA Debug for High Reliability and Functional Safety Designs

Jan 22, 2019 - This webinar introduces Synplify synthesis and its ability to quickly add triple modular redundancy (TMR) to a design.

FPGA Platform – Accelerate FPGA Design, Verification and Debug (Japanese)

Jun 6, 2018 - This webinar will detail how Synopsys solutions provide designers improvements in native integration, automation, runtime acceleration and technology advancements, to achieve the ...

Synopsys FPGA Platform - Enabling Planning to Synthesis

Feb 13, 2018 - This webinar will detail how Synopsys solutions provide designers improvements in native integration, automation, runtime acceleration and technology advancements, to achieve the ...

Best Practices for FPGA Design Coding, Timing and Congestion Reduction

Oct 25, 2017 - This webinar provides tips on design coding, constraint definition, timing closure and how to reduce design congestion for faster turnaround times using Synplify

Enabling Functional Safety for FPGA-based Hardware Design

Jun 28, 2017 - Learn how to automatically “build-in” soft error detection and mitigation with Synopsys Synplify Premier FPGA design tools.