User-friendly Prototyping Tool that Works Directly From Your RTL Source Code and ASIC IP.
Integrated FPGA Design Flow From Planning Through Synthesis
Fast, Reliable Logic Synthesis For Advanced FPGAs and FPGA-based prototypes
Synopsys' tools automate several proven methods for mitigating soft errors such as single-event upsets (SEUs) that are increasingly present in the latest FPGA process geometries.
Simulator-like Visibility Into FPGA Hardware Operation