User-friendly Prototyping Tool that Works Directly From Your RTL Source Code and ASIC IP.
Full-Custom Solution Featuring Visually-assisted Automation Flow
Early RTL Exploration Accelerates Synthesis and Place and Route
Best-in Class Timing, Area, Power, and Test Optimization Correlated with Physical Results
Create a Better Starting Point for Faster Physical Implementation
Next Generation RTL Synthesis Boosts Runtime by 2X and QoR by 5 Percent
Custom Design Formal Equivalence Checking Based on Symbolic Simulation
Synopsys' tools automate several proven methods for mitigating soft errors such as single-event upsets (SEUs) that are increasingly present in the latest FPGA process geometries.
Integrated FPGA Design Flow From Planning Through Synthesis
Predictable RTL-to-GDSII Implementation System Delivers Up To 20 Percent Better Quality-Of-Results