Chip Design Resources

Sort by

Synopsys Suggests

Certify

User-friendly Prototyping Tool that Works Directly From Your RTL Source Code and ASIC IP.

Custom Compiler

Full-Custom Solution Featuring Visually-assisted Automation Flow

DC Explorer

Early RTL Exploration Accelerates Synthesis and Place and Route

DC Ultra

Best-in Class Timing, Area, Power, and Test Optimization Correlated with Physical Results

Design Compiler Graphical

Create a Better Starting Point for Faster Physical Implementation

Design Compiler NXT

Next Generation RTL Synthesis Boosts Runtime by 2X and QoR by 5 Percent

ESP

Custom Design Formal Equivalence Checking Based on Symbolic Simulation

Formality and Formality Ultra

Equivalence Checking for DC Ultra and Design Compiler Graphical

FPGA Design Solution for High-Reliability Applications

Synopsys' tools automate several proven methods for mitigating soft errors such as single-event upsets (SEUs) that are increasingly present in the latest FPGA process geometries.

FPGA Platform

Integrated FPGA Design Flow From Planning Through Synthesis