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Synopsys Suggests


User-friendly Prototyping Tool that Works Directly From Your RTL Source Code and ASIC IP.

Custom Compiler

Full-Custom Solution Featuring Visually-assisted Automation Flow

DC Explorer

Early RTL Exploration Accelerates Synthesis and Place and Route

DC Ultra

Best-in Class Timing, Area, Power, and Test Optimization Correlated with Physical Results

Design Compiler Graphical

Create a Better Starting Point for Faster Physical Implementation

Design Compiler NXT

Next Generation RTL Synthesis Boosts Runtime by 2X and QoR by 5 Percent

DesignWare STAR Hierarchical System

Automated Hierarchical Test Solution for Efficiently Testing SoCs or Designs Using Multiple IP/cores

DesignWare STAR Memory System

Comprehensive, Integrated Test, Repair and Diagnostics Solution That Supports Repairable or Nonrepairable Embedded Memories


Adaptive Scan Compression for Cost-effective DSM Testing


Synthesis-based In-System Self-Test