The Certify prototyping software is a user-friendly tool that works directly from your RTL source code and ASIC IP.
Synopsys' FPGA Platform provides designers an integrated flow from planning through synthesis which helps designers to find and fix bugs earlier.
Best-in Class Timing, Area, Power, and Test Optimization Correlated with Physical Results
Ultra-high Compression for Maximum Test Cost Reduction
Adaptive Scan Compression for Cost-effective DSM Testing
Place and Route Solution For Advanced FinFET Process Technologies
Golden Timing Signoff STA Solution and Environment
Create a Better Starting Point for Faster Physical Implementation
Automated Hierarchical Test Solution for Efficiently Testing SoCs or Designs Using Multiple IP/cores
Synthesis-based In-System Self-Test