Chip Design Resources

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Synopsys Suggests

Certify

The Certify prototyping software is a user-friendly tool that works directly from your RTL source code and ASIC IP.

FPGA Platform

Synopsys' FPGA Platform provides designers an integrated flow from planning through synthesis which helps designers to find and fix bugs earlier.

DC Ultra

Best-in Class Timing, Area, Power, and Test Optimization Correlated with Physical Results

DFTMAX Ultra

Ultra-high Compression for Maximum Test Cost Reduction

DFTMAX

Adaptive Scan Compression for Cost-effective DSM Testing

IC Compiler II

Place and Route Solution For Advanced FinFET Process Technologies

PrimeTime

Golden Timing Signoff STA Solution and Environment

Design Compiler Graphical

Create a Better Starting Point for Faster Physical Implementation

DesignWare STAR Hierarchical System

Automated Hierarchical Test Solution for Efficiently Testing SoCs or Designs Using Multiple IP/cores

DFTMAX LogicBIST

Synthesis-based In-System Self-Test