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Synopsys Suggests

"It's Time for a Change"

Sep 07, 2019 - One Golden-Signoff-Capable Timing Engine to Rule them All.

“Good Enough For Government Work?” Not Anymore.

Jul 31, 2019 - When I was an engineer fresh out of college, I worked for a large defense contractor in southern California. The workplace was filled with employees that worked their whole life with...

3D Extraction Necessities For 5nm And Below

Mar 12, 2018 - For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based ...

A Paradigm Shift With Vertical Nanowire FETs For 5nm And Beyond

Dec 06, 2018 - What moving to the latest transistor types will mean for IC designers.

Analog Design Needs to Change

Apr. 23, 2020 - On their own, better tools aren’t enough to keep pace with analog design challenges.

Be Ready for Emerging Advanced Node PPA Opportunities with Fusion Compiler ...

Today, performance, power and area (PPA) targets are pre-defined values driven by multiple static metrics, including clock and data path timing, power consumption at specific voltage levels and ...

Custom Layout Insights: Analog/Custom Layout Blog

This blog is dedicated to custom layout topics - Graham Etchells

Design Flows At 5nm And Beyond

May 14, 2018 - It’s probably the first time that you’ll ever hear an old (well, old-ish!) person say this, but things were easier back in my day. 40-nanometers was the most advanced node that I ...

EDA Forms the Basis for Designing Secure Systems

Jul 21, 2020 - As Internet of Things (IoT) devices rapidly increase in popularity and deployment, security risks are arising at all levels. It could be at the usability level such as social ...

Enabling a Future of Advanced Node Design Where Uncertainty is a Constant

Mar 01, 2021 - Criteria for devices tested continually changes. How can you turn worst-case scenarios into best case scenarios when designing an SoC?