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Is 5 nm Testing the Same or Different

Apr 11, 2018 - What test methodologies and technologies must be applied to detect all manufacturing defects present in new process nodes such as 5 nm and beyond? If not captured at silicon test ...

The Path to 2nm

Mar 23, 2018 - Diminishing returns may evaporate at 5nm

What to Expect at 5-nm and Beyond and What that Means for EDA

Mar 14, 2018 - With EUV finally on the verge of being inserted into volume manufacturing, let's look at some innovations that have brought us to this point and what ultimately lies ahead for ...

Regain Your Power With Machine Learning

Feb 22, 2018 - How machine learning can help meet PPA challenges and improve ECO optimization productivity

Chip Aging Accelerates

Feb 14, 2018 - As advanced-node chips are added into cars, and usage models shift inside of data centers, new questions surface about reliability.

In-System Automotive Test

Feb 1, 2018 - Chip designers employing in-system BIST techniques to test electronics installed in automobiles.

7/5nm Timing Closure Intensifies

Jan 25, 2018 - The issues may be familiar, but they’re more difficult to solve and can affect everything from performance to yield.

3D Extraction Necessities for 5nm and Below

Jan 25, 2018 - New transistor architectures mean new parasitic effects to watch out for.

Synopsys Integrates Helic’s EM Tools to Tighten Margins on Mixed-signal, ...

Jan 5, 2018 - Synopsys and Helic have integrated Helic's VeloceRF RF device synthesis, RaptorX electromagnetic (EM) modeling and Exalto EM parasitic extraction and sign-off tools with Synopsys' ...

For SoC ISO 26262 Compliance, Should All EDA Tools Be TCL1?

Nov 2, 2017 - Addressing a common misconception about what the safety standard requires.