Jan 25, 2018 - The issues may be familiar, but they’re more difficult to solve and can affect everything from performance to yield.
Jan 25, 2018 - For most of my career in product marketing I’ve been focused on Static Timing Analysis (STA). It was, and still is, an area with a diverse set of topics including graph based ...
Jan 5, 2018 - Synopsys and Helic have integrated Helic's VeloceRF RF device synthesis, RaptorX electromagnetic (EM) modeling and Exalto EM parasitic extraction and sign-off tools with Synopsys' ...
Nov 6, 2017 - Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques...
Dec 2, 2016 - Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
Aug 10, 2016 - New semiconductor technologies like FinFETs are giving rise to new types of fault effects not covered by standard stuck-at and at-speed tests.
Feb 22, 2016 - How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
Jan 11, 2016 - Using triple modular redundancy, error detection and correction, and ‘safe’ FSMs to ensure greater functional safety in FPGA-based designs
Dec 17, 2015 - As FPGAs grow ever bigger and more complex, hard-working synthesis tools are stepping up to help designers find optimum solutions for balancing runtime and quality of results
Dec 10, 2015 - Building Highly Reliable FPGA Designs for Applications Needing Functional Safety