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Synopsys Speeds PrimeTime with AI

Jun 06, 2018 - Synopsys is bringing artifical intelligence to it's PrimeTime signoff tool.

Hierarchical Signoff of SoC Designs at Advanced Process Nodes

Dec 2, 2016 - Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.

Using Sequential Equivalence to Verify Clock-Gating Strategies

Nov 6, 2017 - Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques...

3D Extraction Necessities for 5nm and Below

Jan 25, 2018 - New transistor architectures mean new parasitic effects to watch out for.

Chip Aging Accelerates

Feb 14, 2018 - As advanced-node chips are added into cars, and usage models shift inside of data centers, new questions surface about reliability.

Managing Peak Power

Sep 20, 2017 - Slimmer margins and more data create big challenges for 5G mobile devices, infrastructure and within data centers.

Regain Your Power With Machine Learning

Feb 22, 2018 - How machine learning can help meet PPA challenges and improve ECO optimization productivity

7/5nm Timing Closure Intensifies

Jan 25, 2018 - The issues may be familiar, but they’re more difficult to solve and can affect everything from performance to yield.

Is 5 nm Testing the Same or Different

Apr 11, 2018 - What test methodologies and technologies must be applied to detect all manufacturing defects present in new process nodes such as 5 nm and beyond? If not captured at silicon test ...

What to Expect at 5-nm and Beyond and What that Means for EDA

Mar 14, 2018 - With EUV finally on the verge of being inserted into volume manufacturing, let's look at some innovations that have brought us to this point and what ultimately lies ahead for ...