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Test Automation of 3D Integrated Systems

Jan 2012 - This whitepaper discusses some of the key challenges related to testing 3D integrated systems, and how early adopters can use Synopsys' synthesis-based test solution to maximize their ...

Debugging Non-equivalent Designs Using Formality

It is important to have a basic understanding of how to investigate verification failures in order to get things back on track as quickly as possible. Using debugging tools becomes very important ...

Techniques for Achieving Higher Completion in Formality®

Apr 2011 - Formality is an equivalence-checking solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. Formality delivers superior ...

Synthesis-Based Test For Maximum RTL Designer Productivity

Oct 2010 - Exponential growth in size and complexity of systems on a chip (SoCs), coupled with increasingly stringent quality mandates, necessitates an efficient and productive approach for ...

IC Validator: GDS Merge

Sep 2010 - This paper presents an optimal approach to creating a working snapshot of a design’s complete mask data set for the purposes of in-design physical verification with IC Validator.

Boosting Productivity by Using Look-ahead Constraint Analysis Technology

Aug 2010 - In this paper, we present a unique constraint analysis technology that checks for timing constraints problems and provides an interactive environment with context-sensitive diagnostic ...

StarRC Custom Rapid3D Extraction

Jun 01, 2010 - The next-generation Rapid3D technology in StarRC Custom provides an integrated 3D extraction solution to address these growing accuracy, performance, capacity and ease-of-use needs. ...

StarRC™ Custom: Next-Generation Modeling and Extraction Solution for Custom ...

May 2010 - Custom digital, analog/mixed-signal, and memory designs are particularly sensitive to the nanometer device parameters and parasitics

Testing Low Power Designs with Power Aware Test

Apr 2010 - The most important trend over the past decade for semiconductor design is the dominant requirement to reduce power consumption and power dissipation. Not only do competitive products ...

Achieving Faster Time-to-Tapeout with In-Design Sign-Off Metal Fill

May 2009 - Achieving correct-by-construction results during implementation significantly reduces time to tapeout and avoids schedule delays