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IC Validator Fill

Learn how to execute fill within IC Vaidator

How to compare LVS results using the IC Validator DCV results compare tool

Learn how to compare LVS results using IC Validator DCV results compare tool (RCT). DCV RCT compares extraction stage results separately. You can use DCV RCT to compare only IC Validator LVS ...

Netlist-Versus-Netlist (NVN) in IC Validator

Learn how to compare two netlists of any format like SPICE, IC Validator or VERILOG using NVN utility. An Netlist-Versus-Netlist (NVN) flow varies from an LVS flow in that the NVN does not perform ...

IC Validator NetTran Utility

NetTran is a netlist translation utility. NetTran translates a standard netlist format like SPICE, VERLOG to an IC Validator netlist format, or you can use IC Validator NetTran utility to merge ...

LVS Black Box Flow in IC Validator

LVS Black Box flow allows you to validate top-level designs before all of the building blocks in a top chip level are not completed. Any device data contained within the black box cell is ignored; ...

Edtext File in IC Validator

Learn how to use Edtext file in IC Validator. An Edtext file consists list of text objects that are added to the specified cell on the specified layer number, data type and coordinates on the fly ...

Equivalence File for LVS Run

Learn how to create an equivalence file for LVS run. An equivalence file is used during LVS compare to list each schematic cell and the corresponding layout cell. IC Validator NetTran utility can ...

Extraction or Compare in IC Validator LVS

Learn how to run only extraction or only compare in IC Validator LVS flow.

Layout-Versus-Schematic (LVS) Using IC Validator VUE

Learn how to run Layout-Versus-Schematic (LVS) using IC Validator interactively.

LVS results Comparison Using DCV Results Compare Tool (RCT)

In this video learn how to run Layout-Versus-Schematic (LVS) using IC Validator tool from your shell.