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Enabling Functional Safety for FPGA-based Hardware Design

Jun 28, 2017 - Learn how to automatically “build-in” soft error detection and mitigation with Synopsys Synplify Premier FPGA design tools.

Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate ...

Feb 23, 2016 -This webinar discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how ...

Evolution of Socionext’s Golden UPF Design Flow for Achieving Power Efficiency

Apr 7, 2016 - This webinar will provide details of Socionext’s ever-evolving UPF design flow and their experience with successfully deploying a Golden UPF-based methodology using Synopsys tools.

Evolution of Socionext’s Golden UPF Design Flow for Achieving Power ...

Apr 07, 2016 - This webinar will provide details of Socionext’s ever-evolving UPF design flow and their experience with successfully deploying a Golden UPF-based methodology using Synopsys tools.

Custom Compiler-Visually-assisted Automation for Custom Layout

Apr 21, 2016 - Learn about Synopsys' new full-custom solution that features a visually-assisted automation flow tuned for FinFET-based designs to speed up common design tasks, reduce iterations and...

Xilinx and Synopsys Present: Meeting Test Goals Faster with SpyGlass DFT ADV

Apr 27, 2016 - Early detection of testability issues can prevent major bottlenecks downstream and avoid time-consuming design iterations. In this webinar, Synopsys presents new techniques and ...

Synopsys and ARM Experts Review Smart Constraint Management Practices for ...

May 25, 2016 - Join Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.

Samsung and Synopsys 14nm Physical Verification in IC Validator and In-Design...

Jun 28, 2016 - Samsung and Synopsys together present a webinar on the manufacturing and physical verification challenges and solutions at 14nm.

Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate ...

Feb 23, 2016 - This webinar discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how ...

Sunplus Voltage Drop Analysis Flow: Accelerate Design Closure with Accurate ...

Feb 23, 2016 - This webinar discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how ...