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Floorplanning Complex SoCs with Multiple Levels of Physical Hierarchy articles

Feb 22, 2016 - How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs

FPGA Design For Functional Safety

Jan 11, 2016 - Using triple modular redundancy, error detection and correction, and ‘safe’ FSMs to ensure greater functional safety in FPGA-based designs

Hierarchical Signoff of SoC Designs at Advanced Process Nodes

Dec 2, 2016 - Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.

Getting the most out of IP based FPGA design with Synplify

Feb 27, 2015 - How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices.

Reducing test costs through multisite and concurrent testing

Nov 6, 2015 - How to save test time and test costs by doing more tests in parallel, increasing compression, pooling tester memory, managing branching – and more.

Using Sequential Equivalence to Verify Clock-Gating Strategies

Nov 6, 2017 - Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques...

EDACafe interviews Andy Potemski, Synopsys Group Director for Lynx Design ...

DAC 2016 EDACAFE interview on Lynx’ Design Systems with Synopsys’ own Andy Potemski discussing Lynx’s new capabilities in 2016.03 release which includes full production flow support for IC Compiler...

Custom Layout Insights: Analog/Custom Layout Blog

This blog is dedicated to custom layout topics - Graham Etchells

Looking Past the Horizon

Thinking two steps ahead to address future challenges at 5nm and below

Faster ATPG and Other Test Goodies

Oct 26, 2015 - Synopsys test technology introduced at International Test Conference