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Synopsys Suggests

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform

Feb 2014 - This paper explains how the timing ECO flow delivers fast, predictable, signoff-driven timing closure in a single pass

DFTMAX Compression Shared I/O

Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs

Realizing Advanced P&R Design Utilizing Established Process Nodes

Dec 2013 - Despite the high mindshare garnered by the latest developments at 16nm and 10nm, the fact is that the majority of designs taped out today are at 45nm and above. It is clearly the time to...

PrimeTime Mode Merging – Reducing Analysis cost for Multimode Designs

Oct 2013 - As process technologies shrink, design teams can fit increasing amounts of logic in a single chip, combining functionality that was captured in the past by discrete devices

Introducing DFTMAX Ultra: New Technology to Address Key Test Challenges

Sep 2013 - This paper explains how DFTMAX Ultra delivers new scan compression technology that further reduces test cost and simplifies design impact, providing improvements in test quality

My RTL is an Alien! - Automating ASIC to FPGA-Based Prototype Conversion

Sep 2013 - FPGA-based prototyping is gaining popularity because it provides an economical way to functionally verify an ASIC design by creating a prototype that runs close to "at speed." FPGA-based...

IC Compiler: Multi-Source CTS

Aug 2013 - Multi-source clock tree is a hybrid containing the best aspects of a conventional clock tree and a pure clock mesh. This paper illustrates the benefits such as lower skew and better ...

FinFET Technology – Understanding and Productizing a New Transistor From TSMC...

Apr 2013 - This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution.

Physical Verification of FinFETs and Fully Depleted SOI

Nov 2012 - It has come to be broadly accepted in the semiconductor industry that short-channel effects severely limit bulk planar transistor performance, and alternative device structures will ...

Accelerating 20nm Double Patterning Verification

Oct 2012 - This whitepaper presents the key concepts of DPT compliant design and demonstrates how new signoff technology in IC Validator makes it possible to ensure 20nm manufacturing compliance