Jan 5, 2018 - Synopsys and Helic have integrated Helic's VeloceRF RF device synthesis, RaptorX electromagnetic (EM) modeling and Exalto EM parasitic extraction and sign-off tools with Synopsys' ...
Jul 03, 2018 - Early-access customers talk about their experiences using Fusion Technology enabled portfolio of tools at DAC 2018.
May 2, 2018 - TSMC has certified a tool flow from Synopsys for use on its 7nm FinFET Plus process, which includes steps that demand EUV lithography.
Jun 03, 2015 - Superior Performance and Accuracy, Combined with In-Design Early Analysis Boosts Design Teams' Productivity
Jan 25, 2018 - New transistor architectures mean new parasitic effects to watch out for.
Jan 29, 2018 - Autonomous vehicles will cause fundamental shifts across a number of established industry segments tied to automotive, opening up big opportunities for chips and tools.
Technical tips for IC Validator, design rule checks, layout vs schematic, and hear customers experiences.
Mar 2014 - This paper explains how the timing ECO flow delivers fast, predictable, signoff-driven timing closure in a single pass. It covers a new physically-aware architecture; which runs on a ...
Visually-assisted layout and reliability-aware verification for faster custom design
IC Validator performs physical verification solutions for design rule checking (DRC), layout verification (LVS), and practical DFM applications such as lithography compliance checking (LCC).