Chip Design Resources

Sort by

Synopsys Suggests

Synopsys Integrates Helic’s EM Tools to Tighten Margins on Mixed-signal, ...

Jan 5, 2018 - Synopsys and Helic have integrated Helic's VeloceRF RF device synthesis, RaptorX electromagnetic (EM) modeling and Exalto EM parasitic extraction and sign-off tools with Synopsys' ...

Fusion Improves Timing Say Synopsys Users

Jul 03, 2018 - Early-access customers talk about their experiences using Fusion Technology enabled portfolio of tools at DAC 2018.

TSMC Certifies Synopsys Tool Flow for 7nm EUV Process

May 2, 2018 - TSMC has certified a tool flow from Synopsys for use on its 7nm FinFET Plus process, which includes steps that demand EUV lithography.

Toshiba Standardizes on PrimeRail for Rail Signoff

Jun 03, 2015 - Superior Performance and Accuracy, Combined with In-Design Early Analysis Boosts Design Teams' Productivity

3D Extraction Necessities for 5nm and Below

Jan 25, 2018 - New transistor architectures mean new parasitic effects to watch out for.

Giant Auto Industry Disruption Ahead

Jan 29, 2018 - Autonomous vehicles will cause fundamental shifts across a number of established industry segments tied to automotive, opening up big opportunities for chips and tools.

Videos

Technical tips for IC Validator, design rule checks, layout vs schematic, and hear customers experiences.

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform - ...

Mar 2014 - This paper explains how the timing ECO flow delivers fast, predictable, signoff-driven timing closure in a single pass. It covers a new physically-aware architecture; which runs on a ...

Custom Design Platform

Visually-assisted layout and reliability-aware verification for faster custom design

Physical Verification – IC Validator | Synopsys

IC Validator performs physical verification solutions for design rule checking (DRC), layout verification (LVS), and practical DFM applications such as lithography compliance checking (LCC).