Nov 6, 2017 - Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques...
DAC 2016 EDACAFE interview on Lynx’ Design Systems with Synopsys’ own Andy Potemski discussing Lynx’s new capabilities in 2016.03 release which includes full production flow support for IC Compiler...
This blog is dedicated to custom layout topics - Graham Etchells
Thinking two steps ahead to address future challenges at 5nm and below
Jun 28, 2017 - Learn how to automatically “build-in” soft error detection and mitigation with Synopsys Synplify Premier FPGA design tools.
Jan 25, 2017 - Using Synplify Premier, learn how to setup a design, quickly find RTL compile errors, initially define constraints and tune the design for best performance
May 18, 2017 - Learn how you can immediately use new test point technology in SpyGlass DFT ADV and DFTMAX to reduce ATPG patterns and boost BIST coverage.
Jul 19, 2017 - Using Synplify Premier, learn how to setup a design, quickly find RTL compile errors, initially define constraints and tune the design for best performance.
Sep 14, 2017 - In this webinar, Meena Gupta will discuss how Cavium uses the latest technology in Design Compiler Graphical to achieve superior results while moving to an advanced process node.
Feb 06, 2015 - ARM and Synopsys Collaboration Enables Optimized Implementation of ARM Cortex-A72 Processor-based SoCs with IC Compiler II