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IC Validator and In-Design Metal Fill in IC Compiler II

Nov 2015 - Metal fill has evolved from an afterthought performed by the foundries to a mission critical design requirement that customers now carefully design themselves in order to achieve high ...

FPGA Design Unlimited

May 2015 - Tightly integrated FPGA synthesis and debug tools, such as Synopsys Synplify Premier and Identify RTL Debugger, are needed to help accelerate the time to first hardware with support for ...

Concurrent Clock and Data Optimization with IC Compiler II

Dec 2014 - To advance concurrent clock and data optimization, we need to go beyond incremental enhancements and bolt-on solutions. An optimal solution to CCD needs to provide a fast, convergent, ...

IC Compiler II: 5X Faster Closure on Advanced Designs With Complex MCMM

Dec 2014 - IC Compiler II with its native support for MCMM and MV is the most comprehensive, physical implementation system for advanced designs. It delivers 5X faster throughput, 3X larger ...

IC Compiler II: Finding the Best Floorplan, Fast

Nov 2014 - Today’s designs are large and very complex, requiring hierarchical planning and implementation methodologies. A fast, accurate solution enables design teams to converge on the best ...

Accelerated Optimization with IC Compiler II

Sep 2014 - Efficient optimization is a necessary yet challenging aspect of the physical implementation flow. Newer nodes and growing designs are all conspiring to place growing demands on this ...

Fast, Convergent Clock Synthesis & Optimization with IC Compiler II

Mar 2014 - As more and more challenges from capacity, variability and complexity need to be managed, it is imperative to readdress and rethink both the algorithmic and infrastructural aspects of ...

IC Compiler II: Building a Scalable Platform to Enable the Next 10x in ...

Mar 2014 - Keeping up with the pace demanded by Moore’s law is putting increasingly expanding strains on today’s design planning and physical implementation tools. Merely tweaking existing ...

Advanced Design Planning in IC Compiler II

Mar 2014 - Design exploration and planning is becoming an increasingly critical step of the design creation process as growing constraints and requirements are placed upon it. IC Compiler II has ...

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform - ...

Mar 2014 - This paper explains how the timing ECO flow delivers fast, predictable, signoff-driven timing closure in a single pass. It covers a new physically-aware architecture; which runs on a ...