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Synopsys Suggests

Introducing IC Compiler II

Synopsys’ new place and route system was built from scratch for speed, and incorporates newly developed algorithmic approaches. Hear how this new solution offers un-paralleled improvements in ...

Introduction to TetraMAX II

Antun Domic, Executive VP and GM of the Design Group unveils Synopsys' next-generation ATPG and diagnostics solution.

Juniper Highlights IC Validator’s Performance Benefit: Overnight Full Chip ...

At the IC Validator panel at SNUG Silicon Valley 2018, Juniper shares their experience with IC Validator. Full chip physical verification runtime is a big challenge to designers at the advanced ...

How to Debug, Diagnose and Improve your Synthesis Results

Use Synplify Premier to debug, diagnose, and improve your synthesis results

Lynx at Altera

Learn about how Altera is deploying Lynx Design System as their design automation flow control solution of choice for design.

Lynx Design System QoR Viewer

Learn about how Lynx Design System’s QoR Viewer enables quick access to your pertinent design and flow metrics to facilitate data driven decisions.

How to Minimize the Impact of Metal Fill on Timing?

Metal fill insertion affects timing because of added capacitance. Balancing density requirements and timing on critical nets is crucial for timely design closure. IC Compiler II In-Design with ...

NVIDIA's Experience with IC Validator for Physical Signoff of Full-reticle ...

NVIDIA shares their experience how IC Validator is able to verify large full-reticle GPU designs.

Solving Parasitic Modeling Challenges at 5nm and Below

Technical tips for overcoming parasitic modeling challenges at 5nm and below.

Smarter Signoff Analysis for Advanced Node Multi-Voltage Designs

Achieve fast and more efficient signoff analysis for advanced node multi-voltage designs.