Inductance effects on clock nets can have serious consequences to performance and reliability of today’s advanced process technology designs. In this video, Greg Rollins, principle engineer from ...
Learn how to run IC Validator incremental DRC flow by layer/window options. You can run incremental DRC flow using layer lists, layer numbers or layout window coordinates. The tool outputs only DRC...
You can run only the desired runset checks/functions using run-only command line options. In this video, we will see how to execute a run-only IC Validator job.
Pydb2ascii utility generates an ASCII format error file (.err) from the IC Validator error database PYDB. In this video, we will see how to generate an ASCII format error file from the PYDB database.
Learn about SiliconSmart ADV comprehensive characterization solution for standard cells, I/O, complex cells and memory.
Automated Hierarchical Test Solution for Efficiently Testing SoCs or Designs Using Multiple IP/cores
Aug 23, 2017 - Renesas explains how they use Custom Compiler Co-Design with IC Compiler II in their production design environment to create high-quality shielded nets in in-vehicle CPU and IP modules
Oct 24, 2016 - Platform Certified for Samsung's Second Generation of 10nm Process (10LPP)
Jun 06, 2018 - Synopsys is bringing artifical intelligence to it's PrimeTime signoff tool.
Dec 2, 2016 - Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.