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Platform-Wide Innovations to meet the Challenges of 5-nm and Beyond

The most advanced volume production nodes are 12/10 nanometers, while 8/7 nanometers, both immersion lithography and EUV, are in final stages of development, and will move into volume production soon

Better Modeling of Clock Net Inductance for 7 and 5 Nanometer Designs

Inductance effects on clock nets can have serious consequences to performance and reliability of today’s advanced process technology designs. In this video, Greg Rollins, principle engineer from ...

Smarter Hierarchical Signoff with HyperScale 2nd Generation

HyperScale is changing the way people do signoff! We all know chip sizes are growing like crazy. Moreover, chip sizes are growing at a rate faster than many customers can afford upgraded hardware ...

Smarter Signoff Analysis for Advanced Nodes

In this brief talk, Synopsys R&D will present a smarter solution to achieve fast and more efficient signoff analysis for advanced node multi-voltage designs

Synopsys Highlights at the 2015 International Test Conference

Antun Domic, EVP & GM for the Design Group at Synopsys, discusses exciting new Test-related announcements and Synopsys' activities at the International Test Conference (ITC) 2015.

Unlock IC Compiler II’s “Power of 10X” using Lynx Design System

SNUG Silicon Valley tutorial on use of Lynx with IC Compiler II to implement ARC HS38 Quad Core using TSMC® 16FF+ libraries. (SolvNet login required, use HTML5-compliant browser or set Quicktime as...

Custom Compiler Assistants Webisode Series

short technical webinars focuses on Synopsys’ visually-assisted automation technologies -speeding custom design tasks, reduce iterations & enable reuse

DesignWare STAR Hierarchical System

Automated Hierarchical Test Solution for Efficiently Testing SoCs or Designs Using Multiple IP/cores

Accelerated Synthesis Runtimes Increase Productivity

Dec 17, 2015 - As FPGAs grow ever bigger and more complex, hard-working synthesis tools are stepping up to help designers find optimum solutions for balancing runtime and quality of results

Synopsys and ARM Experts Review Smart Constraint Management Practices for ...

May 25, 2016 - Join Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.