short technical webinars focuses on Synopsys’ visually-assisted automation technologies -speeding custom design tasks, reduce iterations & enable reuse
Automated Hierarchical Test Solution for Efficiently Testing SoCs or Designs Using Multiple IP/cores
Oct 26, 2016 - With TetraMAX II, Synopsys’ next-generation ATPG and diagnostics solution, pattern generation has been re-engineered to deliver unprecedented speed and efficiency.
Aug 23, 2017 - Renesas explains how they use Custom Compiler Co-Design with IC Compiler II in their production design environment to create high-quality shielded nets in in-vehicle CPU and IP modules
Oct 24, 2016 - Platform Certified for Samsung's Second Generation of 10nm Process (10LPP)
Jun 06, 2018 - Synopsys is bringing artifical intelligence to it's PrimeTime signoff tool.
Dec 2, 2016 - Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
Nov 6, 2017 - Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques...
DAC 2016 EDACAFE interview on Lynx’ Design Systems with Synopsys’ own Andy Potemski discussing Lynx’s new capabilities in 2016.03 release which includes full production flow support for IC Compiler...
This blog is dedicated to custom layout topics - Graham Etchells