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Incremental DRC Flow

Learn how to run IC Validator incremental DRC flow by layer/window options. You can run incremental DRC flow using layer lists, layer numbers or layout window coordinates. The tool outputs only DRC...

Run-only IC Validator Command

You can run only the desired runset checks/functions using run-only command line options. In this video, we will see how to execute a run-only IC Validator job.

ASCII Format Error File From the PYDB Database

Pydb2ascii utility generates an ASCII format error file (.err) from the IC Validator error database PYDB. In this video, we will see how to generate an ASCII format error file from the PYDB database.

Golden Signoff Embedded in the RTL-to-GDSII Design Flow with Fusion Compiler

Dr. Henry Sheng, group director of R&D at Synopsys, discusses how Fusion Compiler delivers signoff-accurate PPA on high-performance, low-power designs at advanced nodes, and accelerates design ...

Renesas Case Study: Reducing Custom Net Routing Time by 4X for Automotive ...

Aug 23, 2017 - Renesas explains how they use Custom Compiler Co-Design with IC Compiler II in their production design environment to create high-quality shielded nets in in-vehicle CPU and IP modules

Synopsys' Galaxy Design Platform Enables Superior Low-Power Designs on ...

Oct 24, 2016 - Platform Certified for Samsung's Second Generation of 10nm Process (10LPP)

Synopsys Speeds PrimeTime with AI

Jun 06, 2018 - Synopsys is bringing artifical intelligence to it's PrimeTime signoff tool.

Custom Layout Insights: Analog/Custom Layout Blog

This blog is dedicated to custom layout topics - Graham Etchells

Looking Past the Horizon

Thinking two steps ahead to address future challenges at 5nm and below

Cavium Perspective: Achieving Optimal QoR Faster with Design Compiler Graphical

Sep 14, 2017 - In this webinar, Meena Gupta will discuss how Cavium uses the latest technology in Design Compiler Graphical to achieve superior results while moving to an advanced process node.