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Fusion Compiler Comprehensive RTL-to-GDSII Implementation System

Nov 2018 - The semiconductor industry is going through a renaissance period with waves of technological advancements and innovation...

Fusion Compiler Unified Physical Synthesis

Nov 2018 - Learn about the benefits of Fusion Compiler's unified optimization technologies that is enabling up to 20 percent improved performance, power and area (PPA ), while reducing ...

Functional Safety for FPGA-Based Hardware Designs

Aug 2017 - Learn about the functional safety requirements defined by ISO 26262 for automotive and IEC 61508 for industrial applications that FPGA Designers are incorporating into their designs for ...

Realizing a Scalable Hierarchical Design Flow: What’s Needed for Large Designs

Realizing a Scalable Hierarchical Design Flow: What’s Needed for Large Designs Today’s system on a chip (SoC) designs continue to get larger and more complex. Given that consumer products are now ...

Accurate Signoff Using Path Based Analysis

Path-based analysis is a feature which was introduced in PrimeTime Y-2004.06 release. This technology offers a substantial improvement in static timing analysis accuracy for both PrimeTime and ...

Shift Left Your FPGA Design for Faster Time to Market

Oct 2016 - In just a few short years, FPGAs have become an integral part of system design for many applications either as a co-processor or the main system processor. As FPGA size and performance ...

IC Validator Programmable EERC Mixed Mode Checking Technology

Jun 2016 - A new, comprehensive reliability solution is needed to reduce time to market, improve reliability and ensure longer device operation. This paper is a companion to the introductory IC ...

IC Validator Programmable EERC Netlist Domain Checking Technology

Jun 2016 - Traditional visual inspection or manual checking for electrical rule compliance is both time consuming and error prone. A new, comprehensive reliability solution is needed to reduce time...

Enabling Functional Safety for Industrial IoT, Automotive and Space Applications

Apr 2016 - The increasing interaction of machines with humans is driving the need for industrial and automotive end applications to be functionally safe. The challenge is how best to quickly and ...

IC Compiler II Multi-Level Physical Hierarchy Floorplanning

Jan 2016 - Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a ...