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Synopsys Suggests

IC Validator

Comprehensive Signoff DRC / LVS Tool


Comprehensive Cell, I/O and Memory Characterization

DFTMAX Compression Shared I/O

Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs

StarRC™ Custom: Next-Generation Modeling and Extraction Solution for Custom ...

May 2010 - Custom digital, analog/mixed-signal, and memory designs are particularly sensitive to the nanometer device parameters and parasitics

DC Explorer Demo

Early RTL exploration accelerates synthesis and place & route. - Chris Allsup, Technical Marketing Manager, Synopsys

Smarter Hierarchical Signoff with HyperScale 2nd Generation

HyperScale is changing the way people do signoff! We all know chip sizes are growing like crazy. Moreover, chip sizes are growing at a rate faster than many customers can afford upgraded hardware ...

Synopsys Highlights at the 2015 International Test Conference

Antun Domic, EVP & GM for the Design Group at Synopsys, discusses exciting new Test-related announcements and Synopsys' activities at the International Test Conference (ITC) 2015.

Unlock IC Compiler II’s “Power of 10X” using Lynx Design System

SNUG Silicon Valley tutorial on use of Lynx with IC Compiler II to implement ARC HS38 Quad Core using TSMC® 16FF+ libraries. (SolvNet login required, use HTML5-compliant browser or set Quicktime as...

DesignWare STAR Hierarchical System

Automated Hierarchical Test Solution for Efficiently Testing SoCs or Designs Using Multiple IP/cores

Accelerated Synthesis Runtimes Increase Productivity

Dec 17, 2015 - As FPGAs grow ever bigger and more complex, hard-working synthesis tools are stepping up to help designers find optimum solutions for balancing runtime and quality of results