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Synopsys Suggests

High Throughput GSPS Signal Processing Using Synthesizable IP Cores

Jan 2014 - This whitepaper illustrates how parallel processing synthesizable IP cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient ...

Formality Error-ID Technology Defines Debug Productivity

Have you ever experienced the "now what" anxiety that accompanies a failing equivalence checking verification? Have you found yourself staring at a logic cone with thousands of gates and no clear ...

IC Validator

Comprehensive Signoff DRC / LVS Tool

SiliconSmart

Comprehensive Cell, I/O and Memory Characterization

DFTMAX Compression Shared I/O

Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs

StarRC™ Custom: Next-Generation Modeling and Extraction Solution for Custom ...

May 2010 - Custom digital, analog/mixed-signal, and memory designs are particularly sensitive to the nanometer device parameters and parasitics

DAC 2018 Custom Lunch

Jun 25, 2018 - Advancing Custom/AMS Design for Storage, Automotive, and AI Applications

Innovation Through Technology Leadership and Partnership-Oriented DNA

The most advanced volume production nodes are 12/10 nanometers, while 8/7 nanometers, both immersion lithography and EUV, are in final stages of development, and will move into volume production soon.

Better Modeling of Clock Net Inductance for 7 and 5 Nanometer Designs

Inductance effects on clock nets can have serious consequences to performance and reliability of today’s advanced process technology designs. In this video, Greg Rollins, principle engineer from ...

Smarter Characterization with SiliconSmart ADV All-in-One Product

Learn about SiliconSmart ADV comprehensive characterization solution for standard cells, I/O, complex cells and memory.