Jan 2014 - This whitepaper illustrates how parallel processing synthesizable IP cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient ...
Have you ever experienced the "now what" anxiety that accompanies a failing equivalence checking verification? Have you found yourself staring at a logic cone with thousands of gates and no clear ...
Comprehensive Signoff DRC / LVS Tool
Comprehensive Cell, I/O and Memory Characterization
Nov 2014 - This joint white paper with Arm highlights why shared I/O capability in DFTMAX compression and TetraMAX ATPG is the preferred approach for testing multicore Arm® processor designs
May 2010 - Custom digital, analog/mixed-signal, and memory designs are particularly sensitive to the nanometer device parameters and parasitics
In this video, Synopsys R&D will discuss the most likely options for transistor architectures as we move beyond the 5-nm node and how this is demanding a broader solution of “variability-driven ...
Early RTL exploration accelerates synthesis and place & route. - Chris Allsup, Technical Marketing Manager, Synopsys
The most advanced volume production nodes are 12/10 nanometers, while 8/7 nanometers, both immersion lithography and EUV, are in final stages of development, and will move into volume production soon
In this brief talk, Synopsys R&D will present a smarter solution to achieve fast and more efficient signoff analysis for advanced node multi-voltage designs