FinFETs Race Toward Silicon - EETimes
Mar 10, 2015 - 100+ tapeouts so far include 16nm TSMC chips
Dongbu HiTek Provides Process Design Kits for Synopsys' Custom Compiler Solution
May 02, 2016 - New iPDKs Streamline Development of Analog/Power and Mixed-signal Designs for High-growth Markets
Synopsys’ IC Validator Certified by TowerJazz for Signoff Physical Verification
Jul 19, 2016 - Brings Enhanced Design Productivity for TowerJazz’s Advanced Analog/Mixed-Signal Process Technology
Synopsys IC Validator Physical Signoff Verifies 10 Billion+ Transistors ...
May 11, 2017 - Massively Parallel Architecture Accelerates Physical Signoff and Delivers Industry-Leading Turnaround Time
Synopsys and GLOBALFOUNDRIES Collaborate to Deliver Design Platform and IP ...
Jun 20, 2017 - Enablement Includes Industry-Leading IC Compiler II P&R Solution and DesignWare Embedded Memory IP
Synopsys and Industry Technologists to Address the Path to 2-nm SoC Design
Mar 14, 2018 - Panel Topics Include EUV, High-NA, Metallurgy, and FinFET++
Synopsys Announces Industry’s Most Comprehensive Automotive ISO 26262 ...
Mar 20, 2018 - Certification for Tools and Flows Bolsters Synopsys Position as #1 EDA Provider for Automotive Semiconductor Component and System Designs
Tech Talk: The rationale for fusing together various pieces of a digital design
Tech Talk: What can go wrong with power analysis at advanced nodes
Is 5 nm Testing the Same or Different
Apr 11, 2018 - What test methodologies and technologies must be applied to detect all manufacturing defects present in new process nodes such as 5 nm and beyond? If not captured at silicon test ...